PCem
changeset 11:cb2dbd7b7974
Added missing SiS496 files from last commit.
| author | TomW |
|---|---|
| date | Thu Jul 18 21:20:05 2013 +0100 |
| parents | 9541531878eb |
| children | a87be069d268 |
| files | src/sis496.c src/sis496.h |
| diffstat | 2 files changed, 138 insertions(+), 0 deletions(-) [+] |
line diff
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/src/sis496.c Thu Jul 18 21:20:05 2013 +0100 1.3 @@ -0,0 +1,137 @@ 1.4 +#include <stdlib.h> 1.5 +#include "ibm.h" 1.6 +#include "device.h" 1.7 +#include "io.h" 1.8 +#include "mem.h" 1.9 +#include "pci.h" 1.10 + 1.11 +#include "sis496.h" 1.12 + 1.13 +typedef struct sis496_t 1.14 +{ 1.15 + uint8_t pci_conf[256]; 1.16 +} sis496_t; 1.17 + 1.18 +void sis496_recalcmapping(sis496_t *sis496) 1.19 +{ 1.20 + if (sis496->pci_conf[0x44] & 0x10) 1.21 + { 1.22 + if (sis496->pci_conf[0x45] & 0x01) 1.23 + mem_sethandler(0xe0000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL, NULL); 1.24 + else 1.25 + mem_sethandler(0xe0000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 1.26 + } 1.27 + else 1.28 + mem_sethandler(0xe0000, 0x8000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 1.29 + 1.30 + if (sis496->pci_conf[0x44] & 0x20) 1.31 + { 1.32 + if (sis496->pci_conf[0x45] & 0x01) 1.33 + mem_sethandler(0xe8000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL, NULL); 1.34 + else 1.35 + mem_sethandler(0xe8000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 1.36 + } 1.37 + else 1.38 + mem_sethandler(0xe8000, 0x8000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 1.39 + 1.40 + if (sis496->pci_conf[0x44] & 0x40) 1.41 + { 1.42 + if (sis496->pci_conf[0x45] & 0x01) 1.43 + mem_sethandler(0xf0000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL, NULL); 1.44 + else 1.45 + mem_sethandler(0xf0000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 1.46 + } 1.47 + else 1.48 + mem_sethandler(0xf0000, 0x8000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 1.49 + 1.50 + if (sis496->pci_conf[0x44] & 0x80) 1.51 + { 1.52 + if (sis496->pci_conf[0x45] & 0x01) 1.53 + mem_sethandler(0xf8000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL, NULL); 1.54 + else 1.55 + mem_sethandler(0xf8000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 1.56 + } 1.57 + else 1.58 + mem_sethandler(0xf8000, 0x8000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 1.59 + 1.60 + flushmmucache(); 1.61 + shadowbios = (sis496->pci_conf[0x44] & 0xf0); 1.62 +} 1.63 + 1.64 +void sis496_write(int func, int addr, uint8_t val, void *p) 1.65 +{ 1.66 + sis496_t *sis496 = (sis496_t *)p; 1.67 +pclog("sis496_write : addr=%02x val=%02x\n", addr, val); 1.68 + switch (addr) 1.69 + { 1.70 + case 0x44: /*Shadow configure*/ 1.71 + if ((sis496->pci_conf[0x44] & val) ^ 0xf0) 1.72 + { 1.73 + sis496->pci_conf[0x44] = val; 1.74 + sis496_recalcmapping(sis496); 1.75 + } 1.76 + break; 1.77 + case 0x45: /*Shadow configure*/ 1.78 + //if (val == 3) 1.79 + // output = 3; 1.80 + if ((sis496->pci_conf[0x45] & val) ^ 0x01) 1.81 + { 1.82 + sis496->pci_conf[0x45] = val; 1.83 + sis496_recalcmapping(sis496); 1.84 + } 1.85 + break; 1.86 + } 1.87 + 1.88 + if ((addr >= 4 && addr < 8) || addr >= 0x40) 1.89 + sis496->pci_conf[addr] = val; 1.90 +} 1.91 + 1.92 +uint8_t sis496_read(int func, int addr, void *p) 1.93 +{ 1.94 + sis496_t *sis496 = (sis496_t *)p; 1.95 + 1.96 + return sis496->pci_conf[addr]; 1.97 +} 1.98 + 1.99 +void *sis496_init() 1.100 +{ 1.101 + sis496_t *sis496 = malloc(sizeof(sis496_t)); 1.102 + memset(sis496, 0, sizeof(sis496_t)); 1.103 + 1.104 + pci_add_specific(5, sis496_read, sis496_write, sis496); 1.105 + 1.106 + sis496->pci_conf[0x00] = 0x39; /*SiS*/ 1.107 + sis496->pci_conf[0x01] = 0x10; 1.108 + sis496->pci_conf[0x02] = 0x96; /*496/497*/ 1.109 + sis496->pci_conf[0x03] = 0x04; 1.110 + 1.111 + sis496->pci_conf[0x04] = 7; 1.112 + sis496->pci_conf[0x05] = 0; 1.113 + 1.114 + sis496->pci_conf[0x06] = 0x80; 1.115 + sis496->pci_conf[0x07] = 0x02; 1.116 + 1.117 + sis496->pci_conf[0x08] = 2; /*Device revision*/ 1.118 + 1.119 + sis496->pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/ 1.120 + sis496->pci_conf[0x0a] = 0x00; 1.121 + sis496->pci_conf[0x0b] = 0x06; 1.122 + 1.123 + sis496->pci_conf[0x0e] = 0x00; /*Single function device*/ 1.124 +} 1.125 + 1.126 +void sis496_close(void *p) 1.127 +{ 1.128 + sis496_t *sis496 = (sis496_t *)p; 1.129 + 1.130 + free(sis496); 1.131 +} 1.132 + 1.133 +device_t sis496_device = 1.134 +{ 1.135 + "SiS 496/497", 1.136 + sis496_init, 1.137 + sis496_close, 1.138 + NULL, 1.139 + NULL 1.140 +};