PCem

changeset 143:8523e78e0e48

Fixed default selector in instruction following MOV SS instruction, fixes Windows 3.1 installer
author TomW
date Sat Aug 16 17:36:50 2014 +0100
parents bd46c39a78e8
children 26a55112027e
files src/x86_ops_mov_seg.h
diffstat 1 files changed, 8 insertions(+), 4 deletions(-) [+]
line diff
     1.1 --- a/src/x86_ops_mov_seg.h	Wed Aug 13 20:33:56 2014 +0100
     1.2 +++ b/src/x86_ops_mov_seg.h	Sat Aug 16 17:36:50 2014 +0100
     1.3 @@ -146,7 +146,11 @@
     1.4                  break;
     1.5                  case 0x10: /*SS*/
     1.6                  loadseg(new_seg, &_ss);
     1.7 +                if (abrt) return 0;
     1.8 +                oldpc = pc;
     1.9                  op32 = use32;
    1.10 +                ssegs = 0;
    1.11 +                ea_seg = &_ds;
    1.12                  return 1;
    1.13                  case 0x20: /*FS*/
    1.14                  loadseg(new_seg, &_fs);
    1.15 @@ -177,7 +181,11 @@
    1.16                  break;
    1.17                  case 0x10: /*SS*/
    1.18                  loadseg(new_seg, &_ss);
    1.19 +                if (abrt) return 0;
    1.20 +                oldpc = pc;
    1.21                  op32 = use32;
    1.22 +                ssegs = 0;
    1.23 +                ea_seg = &_ds;
    1.24                  return 1;
    1.25                  case 0x20: /*FS*/
    1.26                  loadseg(new_seg, &_fs);
    1.27 @@ -261,7 +269,6 @@
    1.28          seg = readmemw(easeg, eaaddr + 2);      if (abrt) return 0;
    1.29          loadseg(seg, &_ss);                     if (abrt) return 0;
    1.30          regs[reg].w = addr;
    1.31 -        oldss = ss;
    1.32   
    1.33          cycles -= 7;       
    1.34          return 0;
    1.35 @@ -276,7 +283,6 @@
    1.36          seg = readmemw(easeg, eaaddr + 2);      if (abrt) return 0;
    1.37          loadseg(seg, &_ss);                     if (abrt) return 0;
    1.38          regs[reg].w = addr;
    1.39 -        oldss = ss;
    1.40   
    1.41          cycles -= 7;       
    1.42          return 0;
    1.43 @@ -292,7 +298,6 @@
    1.44          seg = readmemw(easeg, eaaddr + 4);      if (abrt) return 0;
    1.45          loadseg(seg, &_ss);                     if (abrt) return 0;
    1.46          regs[reg].l = addr;
    1.47 -        oldss = ss;
    1.48   
    1.49          cycles -= 7;       
    1.50          return 0;
    1.51 @@ -308,7 +313,6 @@
    1.52          seg = readmemw(easeg, eaaddr + 4);      if (abrt) return 0;
    1.53          loadseg(seg, &_ss);                     if (abrt) return 0;
    1.54          regs[reg].l = addr;
    1.55 -        oldss = ss;
    1.56   
    1.57          cycles -= 7;       
    1.58          return 0;