PCem

changeset 140:3bf6c44c8166

Restricted PIIX PCI config registers. Windows 98 no longer forces drives into compatibility mode.
author TomW
date Thu Jul 31 18:23:40 2014 +0100
parents eee628bf93de
children 7734b12d55f0
files src/piix.c
diffstat 1 files changed, 28 insertions(+), 8 deletions(-) [+]
line diff
     1.1 --- a/src/piix.c	Thu Jul 31 15:57:24 2014 +0100
     1.2 +++ b/src/piix.c	Thu Jul 31 18:23:40 2014 +0100
     1.3 @@ -19,6 +19,7 @@
     1.4  
     1.5  void piix_write(int func, int addr, uint8_t val, void *priv)
     1.6  {
     1.7 +//        pclog("piix_write: func=%d addr=%02x val=%02x %04x:%08x\n", func, addr, val, CS, pc);
     1.8          if (func > 1)
     1.9             return;
    1.10          
    1.11 @@ -26,20 +27,37 @@
    1.12          {
    1.13                  switch (addr)
    1.14                  {
    1.15 -                        case 0x00: case 0x01: case 0x02: case 0x03:
    1.16 -                        case 0x08: case 0x09: case 0x0a: case 0x0b:
    1.17 -                        case 0x0e:
    1.18 -                        return;
    1.19 +                        case 0x04:
    1.20 +                        card_piix_ide[0x04] = (card_piix_ide[0x04] & ~1) | (val & 1);
    1.21 +                        break;
    1.22 +                        case 0x07:
    1.23 +                        card_piix_ide[0x07] = (card_piix_ide[0x07] & ~0x38) | (val & 0x38);
    1.24 +                        break;
    1.25 +                        case 0x0d:
    1.26 +                        card_piix_ide[0x0d] = val;
    1.27 +                        break;
    1.28 +                        
    1.29                          case 0x20:
    1.30 -                        val |= 1;
    1.31 +                        card_piix_ide[0x20] = (val & ~0x0f) | 1;
    1.32 +                        break;
    1.33 +                        case 0x21:
    1.34 +                        card_piix_ide[0x21] = val;
    1.35 +                        break;
    1.36 +                        
    1.37 +                        case 0x40:
    1.38 +                        card_piix_ide[0x40] = val;
    1.39                          break;
    1.40                          case 0x41:
    1.41                          if ((val ^ card_piix_ide[0x41]) & 0x80)
    1.42                          {
    1.43                                  ide_pri_disable();
    1.44                                  if (val & 0x80)
    1.45 -                                   ide_pri_enable();
    1.46 +                                        ide_pri_enable();
    1.47                          }
    1.48 +                        card_piix_ide[0x41] = val;
    1.49 +                        break;
    1.50 +                        case 0x42:
    1.51 +                        card_piix_ide[0x42] = val;
    1.52                          break;
    1.53                          case 0x43:
    1.54                          if ((val ^ card_piix_ide[0x43]) & 0x80)
    1.55 @@ -48,9 +66,9 @@
    1.56                                  if (val & 0x80)
    1.57                                     ide_sec_enable();                                  
    1.58                          }
    1.59 +                        card_piix_ide[0x43] = val;
    1.60                          break;
    1.61                  }
    1.62 -                card_piix_ide[addr] = val;
    1.63                  if ((addr & ~3) == 0x20) /*Bus master base address*/                
    1.64                  {
    1.65                          uint16_t base = (card_piix_ide[0x20] & 0xf0) | (card_piix_ide[0x21] << 8);
    1.66 @@ -74,6 +92,7 @@
    1.67  
    1.68  uint8_t piix_read(int func, int addr, void *priv)
    1.69  {
    1.70 +//        pclog("piix_read: func=%d addr=%02x %04x:%08x\n", func, addr, CS, pc);
    1.71          if (func > 1)
    1.72             return 0xff;
    1.73  
    1.74 @@ -108,7 +127,7 @@
    1.75  void piix_bus_master_write(uint16_t port, uint8_t val, void *priv)
    1.76  {
    1.77          int channel = (port & 8) ? 1 : 0;
    1.78 -//        pclog("PIIX Bus Master write %04X %02X\n", port, val);
    1.79 +//        pclog("PIIX Bus Master write %04X %02X %04x:%08x\n", port, val, CS, pc);
    1.80          switch (port & 7)
    1.81          {
    1.82                  case 0:
    1.83 @@ -144,6 +163,7 @@
    1.84  uint8_t piix_bus_master_read(uint16_t port, void *priv)
    1.85  {
    1.86          int channel = (port & 8) ? 1 : 0;
    1.87 +//        pclog("PIIX Bus Master read %04X %04x:%08x\n", port, CS, pc);
    1.88          switch (port & 7)
    1.89          {
    1.90                  case 0: