PCem
changeset 22:16c3167038d7
Altered device memory mapping.
| author | TomW |
|---|---|
| date | Sat Oct 19 17:06:55 2013 +0100 |
| parents | b162911b1c10 |
| children | 1b2b9acf61eb |
| files | src/808x.c src/ali1429.c src/dma.c src/headland.c src/i430vx.c src/ibm.h src/mem.c src/mem.h src/sis496.c src/um8881f.c src/vid_ati18800.c src/vid_ati28800.c src/vid_ati68860_ramdac.c src/vid_ati_mach64.c src/vid_cga.c src/vid_cga.h src/vid_cl5429.c src/vid_ega.c src/vid_ega.h src/vid_et4000.c src/vid_et4000w32.c src/vid_hercules.c src/vid_mda.c src/vid_olivetti_m24.c src/vid_oti067.c src/vid_paradise.c src/vid_pc1512.c src/vid_pc1640.c src/vid_pc200.c src/vid_s3.c src/vid_s3_virge.c src/vid_sdac_ramdac.c src/vid_stg_ramdac.c src/vid_svga.c src/vid_svga.h src/vid_svga_render.c src/vid_tandy.c src/vid_tkd8001_ramdac.c src/vid_tvga.c src/vid_unk_ramdac.c src/vid_vga.c src/vid_voodoo.c src/video.c |
| diffstat | 43 files changed, 662 insertions(+), 381 deletions(-) [+] |
line diff
1.1 --- a/src/808x.c Sun Oct 13 16:33:43 2013 +0100 1.2 +++ b/src/808x.c Sat Oct 19 17:06:55 2013 +0100 1.3 @@ -487,8 +487,6 @@ 1.4 if (!c) znptable16[c]|=Z_FLAG; 1.5 if (c&0x8000) znptable16[c]|=N_FLAG; 1.6 } 1.7 -// isram[0xF]=1; 1.8 -// printf("isram 0 = %i\n",isram[0]); 1.9 1.10 // makemod1table(); 1.11 } 1.12 @@ -661,6 +659,7 @@ 1.13 loadcs(0xFFFF); 1.14 rammask=0xFFFFFFFF; 1.15 flags=2; 1.16 + makeznptable(); 1.17 initmmucache(); 1.18 resetreadlookup(); 1.19 makemod1table();
2.1 --- a/src/ali1429.c Sun Oct 13 16:33:43 2013 +0100 2.2 +++ b/src/ali1429.c Sat Oct 19 17:06:55 2013 +0100 2.3 @@ -12,44 +12,43 @@ 2.4 void ali1429_write(uint16_t port, uint8_t val, void *priv) 2.5 { 2.6 // return; 2.7 - if (!(port&1)) ali1429_index=val; 2.8 + if (!(port & 1)) 2.9 + ali1429_index = val; 2.10 else 2.11 { 2.12 - ali1429_regs[ali1429_index]=val; 2.13 + ali1429_regs[ali1429_index] = val; 2.14 // pclog("ALI1429 write %02X %02X %04X:%04X %i\n",ali1429_index,val,CS,pc,ins); 2.15 switch (ali1429_index) 2.16 { 2.17 case 0x13: 2.18 -/* if (val == 1) 2.19 - { 2.20 - times = 1; 2.21 - ins = 0; 2.22 - output = 3; 2.23 - }*/ 2.24 -// pclog("write 13 %02X %i\n",val,shadowbios); 2.25 - if (!(val&0xC0)) 2.26 - { 2.27 - shadowbios=0; 2.28 - if (!shadowbios_write) 2.29 - mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, NULL, NULL, NULL, NULL); 2.30 - else 2.31 - mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 2.32 - flushmmucache(); 2.33 - } 2.34 - break; 2.35 + if (!(val & 0xc0)) 2.36 + { 2.37 + shadowbios = 0; 2.38 + if (!shadowbios_write) 2.39 + mem_bios_set_state(0xf0000, 0x10000, 0, 0); 2.40 + else 2.41 + mem_bios_set_state(0xf0000, 0x10000, 0, 1); 2.42 + flushmmucache(); 2.43 + } 2.44 + break; 2.45 case 0x14: 2.46 - shadowbios=val&1;//((val&3)==1); 2.47 - shadowbios_write=val&2; 2.48 + shadowbios = val & 1; 2.49 + shadowbios_write = val & 2; 2.50 switch (val & 3) 2.51 { 2.52 - case 0: mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, NULL, NULL, NULL, NULL); break; 2.53 - case 1: mem_sethandler(0xf0000, 0x10000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL, NULL); break; 2.54 - case 2: mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); break; 2.55 - case 3: mem_sethandler(0xf0000, 0x10000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); break; 2.56 + case 0: 2.57 + mem_bios_set_state(0xf0000, 0x10000, 0, 0); 2.58 + break; 2.59 + case 1: 2.60 + mem_bios_set_state(0xf0000, 0x10000, 1, 0); 2.61 + break; 2.62 + case 2: 2.63 + mem_bios_set_state(0xf0000, 0x10000, 0, 1); 2.64 + break; 2.65 + case 3: 2.66 + mem_bios_set_state(0xf0000, 0x10000, 1, 1); 2.67 + break; 2.68 } 2.69 - 2.70 -// if (val==0x43) shadowbios=1; 2.71 -// pclog("Shadow bios %i\n",shadowbios); 2.72 flushmmucache(); 2.73 break; 2.74 } 2.75 @@ -58,16 +57,17 @@ 2.76 2.77 uint8_t ali1429_read(uint16_t port, void *priv) 2.78 { 2.79 - if (!(port&1)) return ali1429_index; 2.80 + if (!(port & 1)) 2.81 + return ali1429_index; 2.82 if ((ali1429_index >= 0xc0 || ali1429_index == 0x20) && cpu_iscyrix) 2.83 - return 0xff; /*Don't conflict with Cyrix config registers*/ 2.84 + return 0xff; /*Don't conflict with Cyrix config registers*/ 2.85 return ali1429_regs[ali1429_index]; 2.86 } 2.87 2.88 2.89 void ali1429_reset() 2.90 { 2.91 - memset(ali1429_regs,0xFF,256); 2.92 + memset(ali1429_regs, 0xff, 256); 2.93 } 2.94 2.95 void ali1429_init()
3.1 --- a/src/dma.c Sun Oct 13 16:33:43 2013 +0100 3.2 +++ b/src/dma.c Sat Oct 19 17:06:55 2013 +0100 3.3 @@ -3,6 +3,7 @@ 3.4 #include "dma.h" 3.5 #include "fdc.h" 3.6 #include "io.h" 3.7 +#include "mem.h" 3.8 #include "video.h" 3.9 3.10 extern int ins; 3.11 @@ -256,39 +257,12 @@ 3.12 3.13 uint8_t _dma_read(uint32_t addr) 3.14 { 3.15 - switch (addr&0xFFFF8000) 3.16 - { 3.17 -/* case 0xA0000: case 0xA8000: 3.18 - return video_read_a000(addr, NULL); 3.19 - case 0xB0000: 3.20 - return video_read_b000(addr, NULL); 3.21 - case 0xB8000: 3.22 - return video_read_b800(addr, NULL);*/ 3.23 - } 3.24 - if (isram[addr>>16]) return ram[addr]; 3.25 - return 0xff; 3.26 + return mem_readb_phys(addr); 3.27 } 3.28 3.29 void _dma_write(uint32_t addr, uint8_t val) 3.30 { 3.31 - pclog("_dma_write %08X %02X\n", addr, val); 3.32 - switch (addr&0xFFFF8000) 3.33 - { 3.34 -/* case 0xA0000: case 0xA8000: 3.35 - video_write_a000(addr,val, NULL); 3.36 - return; 3.37 - case 0xB0000: 3.38 - video_write_b000(addr,val, NULL); 3.39 - return; 3.40 - case 0xB8000: 3.41 - video_write_b800(addr,val, NULL); 3.42 - return; 3.43 - case 0xC0000: case 0xC8000: case 0xD0000: case 0xD8000: 3.44 - case 0xE0000: case 0xE8000: case 0xF0000: case 0xF8000: 3.45 - return;*/ 3.46 - } 3.47 - if (isram[addr >> 16]) 3.48 - ram[addr] = val; 3.49 + mem_writeb_phys(addr, val); 3.50 } 3.51 /*void writedma2(uint8_t val) 3.52 {
4.1 --- a/src/headland.c Sun Oct 13 16:33:43 2013 +0100 4.2 +++ b/src/headland.c Sat Oct 19 17:06:55 2013 +0100 4.3 @@ -20,12 +20,13 @@ 4.4 shadowbios = val & 0x10; 4.5 shadowbios_write = !(val & 0x10); 4.6 if (shadowbios) 4.7 - mem_sethandler(0xf0000, 0x10000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL , NULL); 4.8 + mem_bios_set_state(0xf0000, 0x10000, 1, 0); 4.9 else 4.10 - mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 4.11 + mem_bios_set_state(0xf0000, 0x10000, 0, 1); 4.12 } 4.13 } 4.14 - else headland_index = val; 4.15 + else 4.16 + headland_index = val; 4.17 } 4.18 4.19 uint8_t headland_read(uint16_t addr, void *priv) 4.20 @@ -33,7 +34,7 @@ 4.21 if (addr & 1) 4.22 { 4.23 if ((headland_index >= 0xc0 || headland_index == 0x20) && cpu_iscyrix) 4.24 - return 0xff; /*Don't conflict with Cyrix config registers*/ 4.25 + return 0xff; /*Don't conflict with Cyrix config registers*/ 4.26 return headland_regs[headland_index]; 4.27 } 4.28 return headland_index;
5.1 --- a/src/i430vx.c Sun Oct 13 16:33:43 2013 +0100 5.2 +++ b/src/i430vx.c Sat Oct 19 17:06:55 2013 +0100 5.3 @@ -13,10 +13,10 @@ 5.4 { 5.5 switch (state & 3) 5.6 { 5.7 - case 0x0: mem_sethandler(addr, size, mem_read_bios, mem_read_biosw, mem_read_biosl, NULL, NULL, NULL , NULL); break; /*DRAM disabled, accesses directed to PCI bus*/ 5.8 - case 0x1: mem_sethandler(addr, size, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL , NULL); break; /*Read only, DRAM write protected, non-cacheable*/ 5.9 - case 0x2: mem_sethandler(addr, size, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); break; /*Write only*/ 5.10 - case 0x3: mem_sethandler(addr, size, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); break; /*Read/write, non-cacheable*/ 5.11 + case 0x0: mem_bios_set_state(addr, size, 0, 0); break; /*DRAM disabled, accesses directed to PCI bus*/ 5.12 + case 0x1: mem_bios_set_state(addr, size, 1, 0); break; /*Read only, DRAM write protected, non-cacheable*/ 5.13 + case 0x2: mem_bios_set_state(addr, size, 0, 1); break; /*Write only*/ 5.14 + case 0x3: mem_bios_set_state(addr, size, 1, 1); break; /*Read/write, non-cacheable*/ 5.15 /*Below are redundant*/ 5.16 // case 0x5: mem_sethandler(addr, size, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL ); break; /*Read only, DRAM write protected, cacheable*/ 5.17 // case 0x7: mem_sethandler(addr, size, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml); break; /*Read/write, non-cacheable*/
6.1 --- a/src/ibm.h Sun Oct 13 16:33:43 2013 +0100 6.2 +++ b/src/ibm.h Sat Oct 19 17:06:55 2013 +0100 6.3 @@ -6,8 +6,6 @@ 6.4 /*Memory*/ 6.5 uint8_t *ram,*vram; 6.6 6.7 -unsigned char isram[0x10000]; 6.8 - 6.9 uint32_t rammask; 6.10 6.11 int readlookup[256],readlookupp[256];
7.1 --- a/src/mem.c Sun Oct 13 16:33:43 2013 +0100 7.2 +++ b/src/mem.c Sat Oct 19 17:06:55 2013 +0100 7.3 @@ -15,21 +15,25 @@ 7.4 #include "x86.h" 7.5 #include "cpu.h" 7.6 7.7 -static uint8_t (*_mem_read_b[0x40000])(uint32_t addr, void *priv); 7.8 -static uint16_t (*_mem_read_w[0x40000])(uint32_t addr, void *priv); 7.9 -static uint32_t (*_mem_read_l[0x40000])(uint32_t addr, void *priv); 7.10 -static void (*_mem_write_b[0x40000])(uint32_t addr, uint8_t val, void *priv); 7.11 -static void (*_mem_write_w[0x40000])(uint32_t addr, uint16_t val, void *priv); 7.12 -static void (*_mem_write_l[0x40000])(uint32_t addr, uint32_t val, void *priv); 7.13 -static void *_mem_priv[0x40000]; 7.14 +static uint8_t (*_mem_read_b[0x40000])(uint32_t addr, void *priv); 7.15 +static uint16_t (*_mem_read_w[0x40000])(uint32_t addr, void *priv); 7.16 +static uint32_t (*_mem_read_l[0x40000])(uint32_t addr, void *priv); 7.17 +static void (*_mem_write_b[0x40000])(uint32_t addr, uint8_t val, void *priv); 7.18 +static void (*_mem_write_w[0x40000])(uint32_t addr, uint16_t val, void *priv); 7.19 +static void (*_mem_write_l[0x40000])(uint32_t addr, uint32_t val, void *priv); 7.20 +static void *_mem_priv[0x40000]; 7.21 +static mem_mapping_t *_mem_mapping[0x40000]; 7.22 + 7.23 +static mem_mapping_t base_mapping; 7.24 +static mem_mapping_t ram_low_mapping; 7.25 +static mem_mapping_t ram_high_mapping; 7.26 +static mem_mapping_t bios_mapping[8]; 7.27 +static mem_mapping_t vrom_mapping; 7.28 +static mem_mapping_t romext_mapping; 7.29 7.30 int shadowbios,shadowbios_write; 7.31 7.32 -uint32_t oldpc; 7.33 -extern uint8_t opcode2; 7.34 -unsigned char isram[0x10000]; 7.35 -extern int ins; 7.36 -extern int timetolive; 7.37 +static unsigned char isram[0x10000]; 7.38 7.39 int mem_size; 7.40 int cache=4; 7.41 @@ -1252,6 +1256,20 @@ 7.42 // pclog("Bad write %08X %08X\n", addr2, val); 7.43 } 7.44 7.45 +uint8_t mem_readb_phys(uint32_t addr) 7.46 +{ 7.47 + if (_mem_read_b[addr >> 14]) 7.48 + return _mem_read_b[addr >> 14](addr, _mem_priv[addr >> 14]); 7.49 + 7.50 + return 0xff; 7.51 +} 7.52 + 7.53 +void mem_writeb_phys(uint32_t addr, uint8_t val) 7.54 +{ 7.55 + if (_mem_write_b[addr >> 14]) 7.56 + _mem_write_b[addr >> 14](addr, val, _mem_priv[addr >> 14]); 7.57 +} 7.58 + 7.59 uint8_t mem_read_ram(uint32_t addr, void *priv) 7.60 { 7.61 // if (addr >= 0xe0000 && addr < 0x100000) pclog("Read RAMb %08X\n", addr); 7.62 @@ -1338,62 +1356,6 @@ 7.63 return *(uint32_t *)&romext[addr & 0x7fff]; 7.64 } 7.65 7.66 -void mem_init() 7.67 -{ 7.68 - int c; 7.69 - ram=malloc(mem_size*1024*1024); 7.70 - rom=malloc(0x20000); 7.71 - vram=malloc(0x800000); 7.72 - vrom=malloc(0x8000); 7.73 - readlookup2=malloc(1024*1024*4); 7.74 - writelookup2=malloc(1024*1024*4); 7.75 - cachelookup2=malloc(1024*1024); 7.76 - biosmask=65535; 7.77 - makeznptable(); 7.78 - memset(ram,0,mem_size*1024*1024); 7.79 - for (c = 0; c < 0x10000; c++) isram[c] = 0; 7.80 - for (c=0;c<(mem_size*16);c++) 7.81 - { 7.82 - isram[c]=1; 7.83 - if (c >= 0xa && c<=0xF) isram[c]=0; 7.84 - } 7.85 - for (c = 0; c < 0x40000; c++) 7.86 - _mem_read_b[c] = _mem_read_w[c] = _mem_read_l[c] = _mem_write_b[c] = _mem_write_w[c] = _mem_write_l[c] = _mem_priv[c] = NULL; 7.87 - 7.88 - mem_sethandler(0x00000, 0xa0000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.89 - if (mem_size > 1) 7.90 - mem_sethandler(0x100000, (mem_size - 1) * 1024 * 1024, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.91 - 7.92 - mem_sethandler(0xc0000, 0x08000, mem_read_vrom, mem_read_vromw, mem_read_vroml, NULL, NULL, NULL, NULL); 7.93 - mem_sethandler(0xc8000, 0x08000, mem_read_romext, mem_read_romextw, mem_read_romextl, NULL, NULL, NULL, NULL); 7.94 - mem_sethandler(0xe0000, 0x20000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.95 -// pclog("Mem resize %i %i\n",mem_size,c); 7.96 -} 7.97 - 7.98 -void mem_resize() 7.99 -{ 7.100 - int c; 7.101 - free(ram); 7.102 - ram=malloc(mem_size*1024*1024); 7.103 - memset(ram,0,mem_size*1024*1024); 7.104 - for (c = 0; c < 0x10000; c++) isram[c] = 0; 7.105 - for (c=0;c<(mem_size*16);c++) 7.106 - { 7.107 - isram[c]=1; 7.108 - if (c >= 0xa && c<=0xF) isram[c]=0; 7.109 - } 7.110 - for (c = 0; c < 0x40000; c++) 7.111 - _mem_read_b[c] = _mem_read_w[c] = _mem_read_l[c] = _mem_write_b[c] = _mem_write_w[c] = _mem_write_l[c] = _mem_priv[c] = NULL; 7.112 - 7.113 - mem_sethandler(0x00000, 0xa0000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.114 - if (mem_size > 1) 7.115 - mem_sethandler(0x100000, (mem_size - 1) * 1024 * 1024, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.116 - 7.117 - mem_sethandler(0xc0000, 0x8000, mem_read_vrom, mem_read_vromw, mem_read_vroml, NULL, NULL, NULL, NULL); 7.118 - mem_sethandler(0xc8000, 0x8000, mem_read_romext, mem_read_romextw, mem_read_romextl, NULL, NULL, NULL, NULL); 7.119 - mem_sethandler(0xe0000, 0x20000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.120 -// pclog("Mem resize %i %i\n",mem_size,c); 7.121 -} 7.122 7.123 void mem_updatecache() 7.124 { 7.125 @@ -1418,64 +1380,267 @@ 7.126 } 7.127 } 7.128 7.129 -void mem_sethandler(uint32_t base, uint32_t size, 7.130 - uint8_t (*read_b)(uint32_t addr, void *priv), 7.131 - uint16_t (*read_w)(uint32_t addr, void *priv), 7.132 - uint32_t (*read_l)(uint32_t addr, void *priv), 7.133 - void (*write_b)(uint32_t addr, uint8_t val, void *priv), 7.134 - void (*write_w)(uint32_t addr, uint16_t val, void *priv), 7.135 - void (*write_l)(uint32_t addr, uint32_t val, void *priv), 7.136 - void *priv) 7.137 +static void mem_mapping_recalc(uint32_t base, uint32_t size) 7.138 { 7.139 uint32_t c; 7.140 -// printf("mem_sethandler : %05X %04X %08X %08X %08X %08X %08X\n", base, size, read_w, write_w, mem_read_biosw, mem_read_ramw, mem_write_ramw); 7.141 + mem_mapping_t *mapping = base_mapping.next; 7.142 + 7.143 + if ((base + size) > 0xffff8000) 7.144 + size = 0xffff0000 - base; 7.145 + 7.146 + /*Clear out old mappings*/ 7.147 for (c = base; c < base + size; c += 0x4000) 7.148 { 7.149 - _mem_read_b[ c >> 14] = read_b; 7.150 - _mem_read_w[ c >> 14] = read_w; 7.151 - _mem_read_l[ c >> 14] = read_l; 7.152 - _mem_write_b[c >> 14] = write_b; 7.153 - _mem_write_w[c >> 14] = write_w; 7.154 - _mem_write_l[c >> 14] = write_l; 7.155 - _mem_priv[c >> 14] = priv; 7.156 + _mem_read_b[c >> 14] = NULL; 7.157 + _mem_read_w[c >> 14] = NULL; 7.158 + _mem_read_l[c >> 14] = NULL; 7.159 + _mem_write_b[c >> 14] = NULL; 7.160 + _mem_write_w[c >> 14] = NULL; 7.161 + _mem_write_l[c >> 14] = NULL; 7.162 + _mem_priv[c >> 14] = NULL; 7.163 + _mem_mapping[c >> 14] = NULL; 7.164 } 7.165 - for (c = base; c < base + size; c += 0x1000) 7.166 +// pclog("mem_mapping_recalc %08X %08X\n", base, size); 7.167 + /*Walk mapping list*/ 7.168 + while (mapping != NULL) 7.169 { 7.170 - readlookup2[c >> 12] = 0xFFFFFFFF; 7.171 - writelookup2[c >> 12] = 0xFFFFFFFF; 7.172 - } 7.173 +// pclog("mapping=%p next=%p base=%08X size=%08X enable=%i\n", mapping, mapping->next, mapping->base, mapping->size, mapping->enable); 7.174 + /*In range?*/ 7.175 + if (mapping->enable && mapping->base < (base + size) && (mapping->base + mapping->size) >= base) 7.176 + { 7.177 + uint32_t start = (mapping->base < base) ? mapping->base : base; 7.178 + uint32_t end = ((mapping->base + mapping->size) < (base + size)) ? (mapping->base + mapping->size) : (base + size); 7.179 + 7.180 + for (c = start; c < end; c += 0x4000) 7.181 + { 7.182 + if (_mem_mapping[c >> 14] == NULL) 7.183 + { 7.184 +// pclog(" Add %08X\n", c); 7.185 + _mem_read_b[c >> 14] = mapping->read_b; 7.186 + _mem_read_w[c >> 14] = mapping->read_w; 7.187 + _mem_read_l[c >> 14] = mapping->read_l; 7.188 + _mem_write_b[c >> 14] = mapping->write_b; 7.189 + _mem_write_w[c >> 14] = mapping->write_w; 7.190 + _mem_write_l[c >> 14] = mapping->write_l; 7.191 + _mem_priv[c >> 14] = mapping->p; 7.192 + _mem_mapping[c >> 14] = mapping; 7.193 + } 7.194 + } 7.195 + } 7.196 + mapping = mapping->next; 7.197 + } 7.198 } 7.199 7.200 -void mem_removehandler(uint32_t base, uint32_t size, 7.201 - uint8_t (*read_b)(uint32_t addr, void *priv), 7.202 - uint16_t (*read_w)(uint32_t addr, void *priv), 7.203 - uint32_t (*read_l)(uint32_t addr, void *priv), 7.204 - void (*write_b)(uint32_t addr, uint8_t val, void *priv), 7.205 - void (*write_w)(uint32_t addr, uint16_t val, void *priv), 7.206 - void (*write_l)(uint32_t addr, uint32_t val, void *priv), 7.207 - void *priv) 7.208 +void mem_mapping_add(mem_mapping_t *mapping, 7.209 + uint32_t base, 7.210 + uint32_t size, 7.211 + uint8_t (*read_b)(uint32_t addr, void *p), 7.212 + uint16_t (*read_w)(uint32_t addr, void *p), 7.213 + uint32_t (*read_l)(uint32_t addr, void *p), 7.214 + void (*write_b)(uint32_t addr, uint8_t val, void *p), 7.215 + void (*write_w)(uint32_t addr, uint16_t val, void *p), 7.216 + void (*write_l)(uint32_t addr, uint32_t val, void *p), 7.217 + void *p) 7.218 +{ 7.219 + mem_mapping_t *dest = &base_mapping; 7.220 + 7.221 + /*Add mapping to the end of the list*/ 7.222 + while (dest->next) 7.223 + dest = dest->next; 7.224 + dest->next = mapping; 7.225 + 7.226 + if (size) 7.227 + mapping->enable = 1; 7.228 + else 7.229 + mapping->enable = 0; 7.230 + mapping->base = base; 7.231 + mapping->size = size; 7.232 + mapping->read_b = read_b; 7.233 + mapping->read_w = read_w; 7.234 + mapping->read_l = read_l; 7.235 + mapping->write_b = write_b; 7.236 + mapping->write_w = write_w; 7.237 + mapping->write_l = write_l; 7.238 + mapping->p = p; 7.239 + mapping->next = NULL; 7.240 + 7.241 + mem_mapping_recalc(mapping->base, mapping->size); 7.242 +} 7.243 + 7.244 +void mem_mapping_set_handler(mem_mapping_t *mapping, 7.245 + uint8_t (*read_b)(uint32_t addr, void *p), 7.246 + uint16_t (*read_w)(uint32_t addr, void *p), 7.247 + uint32_t (*read_l)(uint32_t addr, void *p), 7.248 + void (*write_b)(uint32_t addr, uint8_t val, void *p), 7.249 + void (*write_w)(uint32_t addr, uint16_t val, void *p), 7.250 + void (*write_l)(uint32_t addr, uint32_t val, void *p)) 7.251 +{ 7.252 + mapping->read_b = read_b; 7.253 + mapping->read_w = read_w; 7.254 + mapping->read_l = read_l; 7.255 + mapping->write_b = write_b; 7.256 + mapping->write_w = write_w; 7.257 + mapping->write_l = write_l; 7.258 + 7.259 + mem_mapping_recalc(mapping->base, mapping->size); 7.260 +} 7.261 + 7.262 +void mem_mapping_set_addr(mem_mapping_t *mapping, uint32_t base, uint32_t size) 7.263 +{ 7.264 + /*Remove old mapping*/ 7.265 + mapping->enable = 0; 7.266 + mem_mapping_recalc(mapping->base, mapping->size); 7.267 + 7.268 + /*Set new mapping*/ 7.269 + mapping->enable = 1; 7.270 + mapping->base = base; 7.271 + mapping->size = size; 7.272 + 7.273 + mem_mapping_recalc(mapping->base, mapping->size); 7.274 +} 7.275 + 7.276 +void mem_mapping_set_p(mem_mapping_t *mapping, void *p) 7.277 +{ 7.278 + mapping->p = p; 7.279 +} 7.280 + 7.281 +void mem_mapping_disable(mem_mapping_t *mapping) 7.282 +{ 7.283 + mapping->enable = 0; 7.284 + 7.285 + mem_mapping_recalc(mapping->base, mapping->size); 7.286 +} 7.287 + 7.288 +void mem_mapping_enable(mem_mapping_t *mapping) 7.289 +{ 7.290 + mapping->enable = 1; 7.291 + 7.292 + mem_mapping_recalc(mapping->base, mapping->size); 7.293 +} 7.294 + 7.295 +void mem_init() 7.296 +{ 7.297 + int c; 7.298 + 7.299 + ram = malloc(mem_size * 1024 * 1024); 7.300 + rom = malloc(0x20000); 7.301 + vram = malloc(0x800000); 7.302 + vrom = malloc(0x8000); 7.303 + readlookup2 = malloc(1024 * 1024 * 4); 7.304 + writelookup2 = malloc(1024 * 1024 * 4); 7.305 + cachelookup2 = malloc(1024 * 1024); 7.306 + biosmask = 0xffff; 7.307 + 7.308 + memset(ram, 0, mem_size * 1024 * 1024); 7.309 + 7.310 + memset(isram, 0, sizeof(isram)); 7.311 + for (c = 0; c < (mem_size * 16); c++) 7.312 + { 7.313 + isram[c] = 1; 7.314 + if (c >= 0xa && c <= 0xf) 7.315 + isram[c] = 0; 7.316 + } 7.317 + 7.318 + memset(_mem_read_b, 0, sizeof(_mem_read_b)); 7.319 + memset(_mem_read_w, 0, sizeof(_mem_read_w)); 7.320 + memset(_mem_read_l, 0, sizeof(_mem_read_l)); 7.321 + memset(_mem_write_b, 0, sizeof(_mem_write_b)); 7.322 + memset(_mem_write_w, 0, sizeof(_mem_write_w)); 7.323 + memset(_mem_write_l, 0, sizeof(_mem_write_l)); 7.324 + 7.325 + memset(&base_mapping, 0, sizeof(base_mapping)); 7.326 + 7.327 + mem_mapping_add(&ram_low_mapping, 0x00000, 0xa0000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.328 + if (mem_size > 1) 7.329 + mem_mapping_add(&ram_low_mapping, 0x100000, (mem_size - 1) * 1024 * 1024, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.330 + 7.331 + mem_mapping_add(&bios_mapping[0], 0xe0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.332 + mem_mapping_add(&bios_mapping[1], 0xe4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.333 + mem_mapping_add(&bios_mapping[2], 0xe8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.334 + mem_mapping_add(&bios_mapping[3], 0xec000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.335 + mem_mapping_add(&bios_mapping[4], 0xf0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.336 + mem_mapping_add(&bios_mapping[5], 0xf4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.337 + mem_mapping_add(&bios_mapping[6], 0xf8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.338 + mem_mapping_add(&bios_mapping[7], 0xfc000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.339 + 7.340 + mem_mapping_add(&vrom_mapping, 0xc0000, 0x08000, mem_read_vrom, mem_read_vromw, mem_read_vroml, NULL, NULL, NULL, NULL); 7.341 + mem_mapping_add(&romext_mapping, 0xc8000, 0x08000, mem_read_romext, mem_read_romextw, mem_read_romextl, NULL, NULL, NULL, NULL); 7.342 +// pclog("Mem resize %i %i\n",mem_size,c); 7.343 +} 7.344 + 7.345 +void mem_resize() 7.346 +{ 7.347 + int c; 7.348 + 7.349 + free(ram); 7.350 + ram = malloc(mem_size * 1024 * 1024); 7.351 + memset(ram, 0, mem_size * 1024 * 1024); 7.352 + 7.353 + memset(isram, 0, sizeof(isram)); 7.354 + for (c = 0; c < (mem_size * 16); c++) 7.355 + { 7.356 + isram[c] = 1; 7.357 + if (c >= 0xa && c <= 0xf) 7.358 + isram[c] = 0; 7.359 + } 7.360 + 7.361 + memset(_mem_read_b, 0, sizeof(_mem_read_b)); 7.362 + memset(_mem_read_w, 0, sizeof(_mem_read_w)); 7.363 + memset(_mem_read_l, 0, sizeof(_mem_read_l)); 7.364 + memset(_mem_write_b, 0, sizeof(_mem_write_b)); 7.365 + memset(_mem_write_w, 0, sizeof(_mem_write_w)); 7.366 + memset(_mem_write_l, 0, sizeof(_mem_write_l)); 7.367 + 7.368 + memset(&base_mapping, 0, sizeof(base_mapping)); 7.369 + 7.370 + mem_mapping_add(&ram_low_mapping, 0x00000, 0xa0000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.371 + if (mem_size > 1) 7.372 + mem_mapping_add(&ram_low_mapping, 0x100000, (mem_size - 1) * 1024 * 1024, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.373 + 7.374 + mem_mapping_add(&bios_mapping[0], 0xe0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.375 + mem_mapping_add(&bios_mapping[1], 0xe4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.376 + mem_mapping_add(&bios_mapping[2], 0xe8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.377 + mem_mapping_add(&bios_mapping[3], 0xec000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.378 + mem_mapping_add(&bios_mapping[4], 0xf0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.379 + mem_mapping_add(&bios_mapping[5], 0xf4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.380 + mem_mapping_add(&bios_mapping[6], 0xf8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.381 + mem_mapping_add(&bios_mapping[7], 0xfc000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 7.382 + 7.383 + mem_mapping_add(&vrom_mapping, 0xc0000, 0x08000, mem_read_vrom, mem_read_vromw, mem_read_vroml, NULL, NULL, NULL, NULL); 7.384 + mem_mapping_add(&romext_mapping, 0xc8000, 0x08000, mem_read_romext, mem_read_romextw, mem_read_romextl, NULL, NULL, NULL, NULL); 7.385 + 7.386 +// pclog("Mem resize %i %i\n",mem_size,c); 7.387 +} 7.388 + 7.389 +void mem_bios_set_state(uint32_t base, uint32_t size, int read_ram, int write_ram) 7.390 { 7.391 uint32_t c; 7.392 - if ((base + size) > 0xffff8000) 7.393 - size = 0xffff0000 - base; 7.394 - for (c = base; c < base + size; c += 0x4000) 7.395 + int state = (read_ram ? 1 : 0) | (write_ram ? 2: 0); 7.396 + 7.397 + if (base < 0xe0000 || base > 0xfffff) 7.398 + return; 7.399 + if ((base + size) > 0x100000) 7.400 + size = 0x100000 - base; 7.401 + 7.402 + for (c = base; c < (base + size); c+= 0x4000) 7.403 { 7.404 - if (_mem_priv[c >> 14] == priv) 7.405 +// pclog("mem_bios_set_state: c=%08X base=%08X size=%08X bios=%i\n", c, base, size, (c - 0xe0000) >> 14); 7.406 + switch (state) 7.407 { 7.408 - if ( _mem_read_b[c >> 14] == read_b) _mem_read_b[c >> 14] = NULL; 7.409 - if ( _mem_read_w[c >> 14] == read_w) _mem_read_w[c >> 14] = NULL; 7.410 - if ( _mem_read_l[c >> 14] == read_l) _mem_read_l[c >> 14] = NULL; 7.411 - if (_mem_write_b[c >> 14] == write_b) _mem_write_b[c >> 14] = NULL; 7.412 - if (_mem_write_w[c >> 14] == write_w) _mem_write_w[c >> 14] = NULL; 7.413 - if (_mem_write_l[c >> 14] == write_l) _mem_write_l[c >> 14] = NULL; 7.414 - _mem_priv[c >> 14] = NULL; 7.415 + case 0: 7.416 + mem_mapping_set_handler(&bios_mapping[(c - 0xe0000) >> 14], mem_read_bios, mem_read_biosw, mem_read_biosl, NULL, NULL, NULL); 7.417 + break; 7.418 + case 1: 7.419 + mem_mapping_set_handler(&bios_mapping[(c - 0xe0000) >> 14], mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL); 7.420 + break; 7.421 + case 2: 7.422 + mem_mapping_set_handler(&bios_mapping[(c - 0xe0000) >> 14], mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml); 7.423 + break; 7.424 + case 3: 7.425 + mem_mapping_set_handler(&bios_mapping[(c - 0xe0000) >> 14], mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml); 7.426 + break; 7.427 } 7.428 } 7.429 - for (c = base; c < base + size; c += 0x1000) 7.430 - { 7.431 - readlookup2[c >> 12] = 0xFFFFFFFF; 7.432 - writelookup2[c >> 12] = 0xFFFFFFFF; 7.433 - } 7.434 } 7.435 7.436 int mem_a20_key = 0, mem_a20_alt = 0;
8.1 --- a/src/mem.h Sun Oct 13 16:33:43 2013 +0100 8.2 +++ b/src/mem.h Sat Oct 19 17:06:55 2013 +0100 8.3 @@ -1,3 +1,22 @@ 8.4 +typedef struct mem_mapping_t 8.5 +{ 8.6 + struct mem_mapping_t *prev, *next; 8.7 + 8.8 + int enable; 8.9 + 8.10 + uint32_t base; 8.11 + uint32_t size; 8.12 + 8.13 + uint8_t (*read_b)(uint32_t addr, void *priv); 8.14 + uint16_t (*read_w)(uint32_t addr, void *priv); 8.15 + uint32_t (*read_l)(uint32_t addr, void *priv); 8.16 + void (*write_b)(uint32_t addr, uint8_t val, void *priv); 8.17 + void (*write_w)(uint32_t addr, uint16_t val, void *priv); 8.18 + void (*write_l)(uint32_t addr, uint32_t val, void *priv); 8.19 + 8.20 + void *p; 8.21 +} mem_mapping_t; 8.22 + 8.23 extern uint8_t *ram,*rom,*vram,*vrom; 8.24 extern uint8_t romext[32768]; 8.25 extern int readlnum,writelnum; 8.26 @@ -6,27 +25,37 @@ 8.27 extern int cache; 8.28 extern int memwaitstate; 8.29 8.30 -void mem_sethandler(uint32_t base, uint32_t size, 8.31 - uint8_t (*read_b)(uint32_t addr, void *priv), 8.32 - uint16_t (*read_w)(uint32_t addr, void *priv), 8.33 - uint32_t (*read_l)(uint32_t addr, void *priv), 8.34 - void (*write_b)(uint32_t addr, uint8_t val, void *priv), 8.35 - void (*write_w)(uint32_t addr, uint16_t val, void *priv), 8.36 - void (*write_l)(uint32_t addr, uint32_t val, void *priv), 8.37 - void *priv); 8.38 +void mem_mapping_add(mem_mapping_t *mapping, 8.39 + uint32_t base, 8.40 + uint32_t size, 8.41 + uint8_t (*read_b)(uint32_t addr, void *p), 8.42 + uint16_t (*read_w)(uint32_t addr, void *p), 8.43 + uint32_t (*read_l)(uint32_t addr, void *p), 8.44 + void (*write_b)(uint32_t addr, uint8_t val, void *p), 8.45 + void (*write_w)(uint32_t addr, uint16_t val, void *p), 8.46 + void (*write_l)(uint32_t addr, uint32_t val, void *p), 8.47 + void *p); 8.48 +void mem_mapping_set_handler(mem_mapping_t *mapping, 8.49 + uint8_t (*read_b)(uint32_t addr, void *p), 8.50 + uint16_t (*read_w)(uint32_t addr, void *p), 8.51 + uint32_t (*read_l)(uint32_t addr, void *p), 8.52 + void (*write_b)(uint32_t addr, uint8_t val, void *p), 8.53 + void (*write_w)(uint32_t addr, uint16_t val, void *p), 8.54 + void (*write_l)(uint32_t addr, uint32_t val, void *p)); 8.55 +void mem_mapping_set_p(mem_mapping_t *mapping, void *p); 8.56 +void mem_mapping_set_addr(mem_mapping_t *mapping, uint32_t base, uint32_t size); 8.57 +void mem_mapping_disable(mem_mapping_t *mapping); 8.58 +void mem_mapping_enable(mem_mapping_t *mapping); 8.59 8.60 -void mem_removehandler(uint32_t base, uint32_t size, 8.61 - uint8_t (*read_b)(uint32_t addr, void *priv), 8.62 - uint16_t (*read_w)(uint32_t addr, void *priv), 8.63 - uint32_t (*read_l)(uint32_t addr, void *priv), 8.64 - void (*write_b)(uint32_t addr, uint8_t val, void *priv), 8.65 - void (*write_w)(uint32_t addr, uint16_t val, void *priv), 8.66 - void (*write_l)(uint32_t addr, uint32_t val, void *priv), 8.67 - void *priv); 8.68 +void mem_bios_set_state(uint32_t base, uint32_t size, int read_ram, int write_ram); 8.69 + 8.70 extern int mem_a20_alt; 8.71 extern int mem_a20_key; 8.72 void mem_a20_recalc(); 8.73 8.74 +uint8_t mem_readb_phys(uint32_t addr); 8.75 +void mem_writeb_phys(uint32_t addr, uint8_t val); 8.76 + 8.77 uint8_t mem_read_ram(uint32_t addr, void *priv); 8.78 uint16_t mem_read_ramw(uint32_t addr, void *priv); 8.79 uint32_t mem_read_raml(uint32_t addr, void *priv);
9.1 --- a/src/sis496.c Sun Oct 13 16:33:43 2013 +0100 9.2 +++ b/src/sis496.c Sat Oct 19 17:06:55 2013 +0100 9.3 @@ -17,42 +17,42 @@ 9.4 if (sis496->pci_conf[0x44] & 0x10) 9.5 { 9.6 if (sis496->pci_conf[0x45] & 0x01) 9.7 - mem_sethandler(0xe0000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL, NULL); 9.8 + mem_bios_set_state(0xe0000, 0x08000, 1, 0); 9.9 else 9.10 - mem_sethandler(0xe0000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 9.11 + mem_bios_set_state(0xe0000, 0x08000, 1, 1); 9.12 } 9.13 else 9.14 - mem_sethandler(0xe0000, 0x8000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 9.15 + mem_bios_set_state(0xe0000, 0x08000, 0, 1); 9.16 9.17 if (sis496->pci_conf[0x44] & 0x20) 9.18 { 9.19 if (sis496->pci_conf[0x45] & 0x01) 9.20 - mem_sethandler(0xe8000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL, NULL); 9.21 + mem_bios_set_state(0xe8000, 0x08000, 1, 0); 9.22 else 9.23 - mem_sethandler(0xe8000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 9.24 + mem_bios_set_state(0xe8000, 0x08000, 1, 1); 9.25 } 9.26 else 9.27 - mem_sethandler(0xe8000, 0x8000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 9.28 + mem_bios_set_state(0xe8000, 0x08000, 0, 1); 9.29 9.30 if (sis496->pci_conf[0x44] & 0x40) 9.31 { 9.32 if (sis496->pci_conf[0x45] & 0x01) 9.33 - mem_sethandler(0xf0000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL, NULL); 9.34 + mem_bios_set_state(0xf0000, 0x08000, 1, 0); 9.35 else 9.36 - mem_sethandler(0xf0000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 9.37 + mem_bios_set_state(0xf0000, 0x08000, 1, 1); 9.38 } 9.39 else 9.40 - mem_sethandler(0xf0000, 0x8000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 9.41 + mem_bios_set_state(0xf0000, 0x08000, 0, 1); 9.42 9.43 if (sis496->pci_conf[0x44] & 0x80) 9.44 { 9.45 if (sis496->pci_conf[0x45] & 0x01) 9.46 - mem_sethandler(0xf8000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL, NULL); 9.47 + mem_bios_set_state(0xf8000, 0x08000, 1, 0); 9.48 else 9.49 - mem_sethandler(0xf8000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 9.50 + mem_bios_set_state(0xf8000, 0x08000, 1, 1); 9.51 } 9.52 else 9.53 - mem_sethandler(0xf8000, 0x8000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 9.54 + mem_bios_set_state(0xf8000, 0x08000, 0, 1); 9.55 9.56 flushmmucache(); 9.57 shadowbios = (sis496->pci_conf[0x44] & 0xf0);
10.1 --- a/src/um8881f.c Sun Oct 13 16:33:43 2013 +0100 10.2 +++ b/src/um8881f.c Sat Oct 19 17:06:55 2013 +0100 10.3 @@ -15,9 +15,9 @@ 10.4 if ((card_16[0x54] ^ val) & 0x01) 10.5 { 10.6 if (val & 1) 10.7 - mem_sethandler(0xe0000, 0x10000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); 10.8 + mem_bios_set_state(0xe0000, 0x10000, 1, 1); 10.9 else 10.10 - mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, NULL, NULL, NULL , NULL); 10.11 + mem_bios_set_state(0xe0000, 0x10000, 0, 0); 10.12 } 10.13 flushmmucache_nopc(); 10.14 } 10.15 @@ -27,10 +27,10 @@ 10.16 { 10.17 switch (val & 0xc0) 10.18 { 10.19 - case 0x00: mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); break; 10.20 - case 0x40: mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, NULL, NULL, NULL , NULL); break; 10.21 - case 0x80: mem_sethandler(0xf0000, 0x10000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); break; 10.22 - case 0xc0: mem_sethandler(0xf0000, 0x10000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL , NULL); break; 10.23 + case 0x00: mem_bios_set_state(0xf0000, 0x10000, 0, 1); break; 10.24 + case 0x40: mem_bios_set_state(0xf0000, 0x10000, 0, 0); break; 10.25 + case 0x80: mem_bios_set_state(0xf0000, 0x10000, 1, 1); break; 10.26 + case 0xc0: mem_bios_set_state(0xf0000, 0x10000, 1, 0); break; 10.27 } 10.28 shadowbios = val & 0x80; 10.29 shadowbios_write = !(val & 0x40); 10.30 @@ -56,9 +56,7 @@ 10.31 { 10.32 return card_18[addr]; 10.33 } 10.34 - 10.35 - 10.36 - 10.37 + 10.38 void um8881f_init() 10.39 { 10.40 pci_add_specific(16, um8881f_read, um8881f_write, NULL);
11.1 --- a/src/vid_ati18800.c Sun Oct 13 16:33:43 2013 +0100 11.2 +++ b/src/vid_ati18800.c Sat Oct 19 17:06:55 2013 +0100 11.3 @@ -3,6 +3,7 @@ 11.4 #include "ibm.h" 11.5 #include "device.h" 11.6 #include "io.h" 11.7 +#include "mem.h" 11.8 #include "video.h" 11.9 #include "vid_ati18800.h" 11.10 #include "vid_ati_eeprom.h"
12.1 --- a/src/vid_ati28800.c Sun Oct 13 16:33:43 2013 +0100 12.2 +++ b/src/vid_ati28800.c Sat Oct 19 17:06:55 2013 +0100 12.3 @@ -3,6 +3,7 @@ 12.4 #include "ibm.h" 12.5 #include "device.h" 12.6 #include "io.h" 12.7 +#include "mem.h" 12.8 #include "video.h" 12.9 #include "vid_ati28800.h" 12.10 #include "vid_ati_eeprom.h"
13.1 --- a/src/vid_ati68860_ramdac.c Sun Oct 13 16:33:43 2013 +0100 13.2 +++ b/src/vid_ati68860_ramdac.c Sat Oct 19 17:06:55 2013 +0100 13.3 @@ -19,6 +19,7 @@ 13.4 7 If set can remove "snow" in some cases (A860_Delay_L ?) ?? 13.5 */ 13.6 #include "ibm.h" 13.7 +#include "mem.h" 13.8 #include "video.h" 13.9 #include "vid_svga.h" 13.10 #include "vid_ati68860_ramdac.h"
14.1 --- a/src/vid_ati_mach64.c Sun Oct 13 16:33:43 2013 +0100 14.2 +++ b/src/vid_ati_mach64.c Sat Oct 19 17:06:55 2013 +0100 14.3 @@ -16,6 +16,10 @@ 14.4 14.5 typedef struct mach64_t 14.6 { 14.7 + mem_mapping_t linear_mapping; 14.8 + mem_mapping_t mmio_mapping; 14.9 + mem_mapping_t mmio_linear_mapping; 14.10 + 14.11 ati68860_ramdac_t ramdac; 14.12 ati_eeprom_t eeprom; 14.13 ics2595_t ics2595; 14.14 @@ -321,38 +325,43 @@ 14.15 void mach64_updatemapping(mach64_t *mach64) 14.16 { 14.17 svga_t *svga = &mach64->svga; 14.18 - mem_removehandler(0xa0000, 0x10000, mach64_read, NULL, NULL, mach64_write, NULL, NULL, mach64); 14.19 - mem_removehandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 14.20 - mem_removehandler(0xbc000, 0x04000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, mach64); 14.21 - if (mach64->old_linear_base >= (mem_size << 20)) 14.22 - { 14.23 - mem_removehandler(mach64->old_linear_base, (8 << 20) - 0x4000, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); 14.24 - mem_removehandler(mach64->old_linear_base + ((8 << 20) - 0x4000), 0x4000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, mach64); 14.25 - } 14.26 + 14.27 + mem_mapping_disable(&mach64->mmio_mapping); 14.28 // pclog("Write mapping %02X\n", val); 14.29 switch (svga->gdcreg[6] & 0xc) 14.30 { 14.31 case 0x0: /*128k at A0000*/ 14.32 - mem_sethandler(0xa0000, 0x10000, mach64_read, NULL, NULL, mach64_write, NULL, NULL, mach64); 14.33 - mem_sethandler(0xbc000, 0x04000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, mach64); 14.34 + mem_mapping_set_handler(&mach64->svga.mapping, mach64_read, NULL, NULL, mach64_write, NULL, NULL); 14.35 + mem_mapping_set_p(&mach64->svga.mapping, mach64); 14.36 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000); 14.37 + mem_mapping_enable(&mach64->mmio_mapping); 14.38 break; 14.39 case 0x4: /*64k at A0000*/ 14.40 - mem_sethandler(0xa0000, 0x10000, mach64_read, NULL, NULL, mach64_write, NULL, NULL, mach64); 14.41 + mem_mapping_set_handler(&mach64->svga.mapping, mach64_read, NULL, NULL, mach64_write, NULL, NULL); 14.42 + mem_mapping_set_p(&mach64->svga.mapping, mach64); 14.43 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); 14.44 break; 14.45 case 0x8: /*32k at B0000*/ 14.46 - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 14.47 + mem_mapping_set_handler(&mach64->svga.mapping, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel); 14.48 + mem_mapping_set_p(&mach64->svga.mapping, svga); 14.49 + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); 14.50 break; 14.51 case 0xC: /*32k at B8000*/ 14.52 - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 14.53 + mem_mapping_set_handler(&mach64->svga.mapping, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel); 14.54 + mem_mapping_set_p(&mach64->svga.mapping, svga); 14.55 + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); 14.56 break; 14.57 } 14.58 - if (mach64->linear_base >= (mem_size << 20)) 14.59 + if (mach64->linear_base) 14.60 { 14.61 - mem_sethandler(mach64->linear_base, (8 << 20) - 0x4000, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); 14.62 - mem_sethandler(mach64->linear_base + ((8 << 20) - 0x4000), 0x4000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, mach64); 14.63 -// pclog("Mach64 LFB %08X\n", mach64->linear_base); 14.64 + mem_mapping_set_addr(&mach64->linear_mapping, mach64->linear_base, (8 << 20) - 0x4000); 14.65 + mem_mapping_set_addr(&mach64->mmio_linear_mapping, mach64->linear_base + ((8 << 20) - 0x4000), 0x4000); 14.66 } 14.67 - mach64->old_linear_base = mach64->linear_base; 14.68 + else 14.69 + { 14.70 + mem_mapping_disable(&mach64->linear_mapping); 14.71 + mem_mapping_disable(&mach64->mmio_linear_mapping); 14.72 + } 14.73 } 14.74 14.75 #define READ8(addr, var) switch ((addr) & 3) \ 14.76 @@ -2019,6 +2028,11 @@ 14.77 mach64_in, mach64_out, 14.78 mach64_hwcursor_draw); 14.79 14.80 + mem_mapping_add(&mach64->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &mach64->svga); 14.81 + mem_mapping_add(&mach64->mmio_linear_mapping, 0, 0, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, mach64); 14.82 + mem_mapping_add(&mach64->mmio_mapping, 0xbc000, 0x04000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, mach64); 14.83 + mem_mapping_disable(&mach64->mmio_mapping); 14.84 + 14.85 io_sethandler(0x03c0, 0x0020, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64); 14.86 14.87 for (c = 0; c < 8; c++)
15.1 --- a/src/vid_cga.c Sun Oct 13 16:33:43 2013 +0100 15.2 +++ b/src/vid_cga.c Sat Oct 19 17:06:55 2013 +0100 15.3 @@ -497,7 +497,7 @@ 15.4 q_filt[c] = 512.0 * sin((3.14 * (cga_tint + c * 4) / 16.0) - 33.0 / 180.0); 15.5 } 15.6 timer_add(cga_poll, &cga->vidtime, TIMER_ALWAYS_ENABLED, cga); 15.7 - mem_sethandler(0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, cga); 15.8 + mem_mapping_add(&cga->mapping, 0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, cga); 15.9 io_sethandler(0x03d0, 0x0010, cga_in, NULL, NULL, cga_out, NULL, NULL, cga); 15.10 return cga; 15.11 }
16.1 --- a/src/vid_cga.h Sun Oct 13 16:33:43 2013 +0100 16.2 +++ b/src/vid_cga.h Sat Oct 19 17:06:55 2013 +0100 16.3 @@ -1,5 +1,7 @@ 16.4 typedef struct cga_t 16.5 { 16.6 + mem_mapping_t mapping; 16.7 + 16.8 int crtcreg; 16.9 uint8_t crtc[32]; 16.10
17.1 --- a/src/vid_cl5429.c Sun Oct 13 16:33:43 2013 +0100 17.2 +++ b/src/vid_cl5429.c Sat Oct 19 17:06:55 2013 +0100 17.3 @@ -12,6 +12,8 @@ 17.4 17.5 typedef struct gd5429_t 17.6 { 17.7 + mem_mapping_t mmio_mapping; 17.8 + 17.9 svga_t svga; 17.10 17.11 uint32_t bank[2]; 17.12 @@ -220,25 +222,25 @@ 17.13 { 17.14 svga_t *svga = &gd5429->svga; 17.15 17.16 - mem_removehandler(0xa0000, 0x20000, gd5429_read, NULL, NULL, gd5429_write, NULL, NULL, gd5429); 17.17 - mem_removehandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 17.18 - mem_removehandler(0xb8000, 0x00100, gd5429_mmio_read, NULL, NULL, gd5429_mmio_write, NULL, NULL, gd5429); 17.19 pclog("Write mapping %02X %i\n", svga->gdcreg[6], svga->seqregs[0x17] & 0x04); 17.20 switch (svga->gdcreg[6] & 0x0C) 17.21 { 17.22 case 0x0: /*128k at A0000*/ 17.23 - mem_sethandler(0xa0000, 0x10000, gd5429_read, NULL, NULL, gd5429_write, NULL, NULL, gd5429); 17.24 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); 17.25 + mem_mapping_disable(&gd5429->mmio_mapping); 17.26 break; 17.27 case 0x4: /*64k at A0000*/ 17.28 - mem_sethandler(0xa0000, 0x10000, gd5429_read, NULL, NULL, gd5429_write, NULL, NULL, gd5429); 17.29 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); 17.30 if (svga->seqregs[0x17] & 0x04) 17.31 - mem_sethandler(0xb8000, 0x00100, gd5429_mmio_read, NULL, NULL, gd5429_mmio_write, NULL, NULL, gd5429); 17.32 + mem_mapping_set_addr(&gd5429->mmio_mapping, 0xb8000, 0x00100); 17.33 break; 17.34 case 0x8: /*32k at B0000*/ 17.35 - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 17.36 + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); 17.37 + mem_mapping_disable(&gd5429->mmio_mapping); 17.38 break; 17.39 case 0xC: /*32k at B8000*/ 17.40 - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 17.41 + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); 17.42 + mem_mapping_disable(&gd5429->mmio_mapping); 17.43 break; 17.44 } 17.45 } 17.46 @@ -539,13 +541,14 @@ 17.47 if (gd5429->blt.mode & 0x04) 17.48 { 17.49 // pclog("blt.mode & 0x04\n"); 17.50 - mem_removehandler(0xa0000, 0x10000, gd5429_read, NULL, NULL, gd5429_write, NULL, NULL, gd5429); 17.51 - mem_sethandler(0xa0000, 0x10000, NULL, NULL, NULL, NULL, gd5429_blt_write_w, gd5429_blt_write_l, gd5429); 17.52 + mem_mapping_set_handler(&svga->mapping, NULL, NULL, NULL, NULL, gd5429_blt_write_w, gd5429_blt_write_l); 17.53 + mem_mapping_set_p(&svga->mapping, gd5429); 17.54 return; 17.55 } 17.56 else 17.57 { 17.58 - mem_removehandler(0xa0000, 0x10000, NULL, NULL, NULL, NULL, gd5429_blt_write_w, gd5429_blt_write_l, gd5429); 17.59 + mem_mapping_set_handler(&gd5429->svga.mapping, gd5429_read, NULL, NULL, gd5429_write, NULL, NULL); 17.60 + mem_mapping_set_p(&gd5429->svga.mapping, gd5429); 17.61 gd5429_recalc_mapping(gd5429); 17.62 } 17.63 } 17.64 @@ -666,7 +669,8 @@ 17.65 { 17.66 if (gd5429->blt.mode & 0x04) 17.67 { 17.68 - mem_removehandler(0xa0000, 0x10000, NULL, NULL, NULL, NULL, gd5429_blt_write_w, gd5429_blt_write_l, gd5429); 17.69 + mem_mapping_set_handler(&gd5429->svga.mapping, gd5429_read, NULL, NULL, gd5429_write, NULL, NULL); 17.70 + mem_mapping_set_p(&gd5429->svga.mapping, gd5429); 17.71 gd5429_recalc_mapping(gd5429); 17.72 } 17.73 return; 17.74 @@ -808,6 +812,11 @@ 17.75 gd5429_in, gd5429_out, 17.76 gd5429_hwcursor_draw); 17.77 17.78 + mem_mapping_set_handler(&gd5429->svga.mapping, gd5429_read, NULL, NULL, gd5429_write, NULL, NULL); 17.79 + mem_mapping_set_p(&gd5429->svga.mapping, gd5429); 17.80 + 17.81 + mem_mapping_add(&gd5429->mmio_mapping, 0, 0, gd5429_mmio_read, NULL, NULL, gd5429_mmio_write, NULL, NULL, gd5429); 17.82 + 17.83 io_sethandler(0x03c0, 0x0020, gd5429_in, NULL, NULL, gd5429_out, NULL, NULL, gd5429); 17.84 17.85 svga->hwcursor.yoff = 32;
18.1 --- a/src/vid_ega.c Sun Oct 13 16:33:43 2013 +0100 18.2 +++ b/src/vid_ega.c Sat Oct 19 17:06:55 2013 +0100 18.3 @@ -96,21 +96,20 @@ 18.4 ega->readmode = val & 8; 18.5 break; 18.6 case 6: 18.7 - mem_removehandler(0xa0000, 0x20000, ega_read, NULL, NULL, ega_write, NULL, NULL, ega); 18.8 // pclog("Write mapping %02X\n", val); 18.9 switch (val & 0xc) 18.10 { 18.11 case 0x0: /*128k at A0000*/ 18.12 - mem_sethandler(0xa0000, 0x20000, ega_read, NULL, NULL, ega_write, NULL, NULL, ega); 18.13 + mem_mapping_set_addr(&ega->mapping, 0xa0000, 0x20000); 18.14 break; 18.15 case 0x4: /*64k at A0000*/ 18.16 - mem_sethandler(0xa0000, 0x10000, ega_read, NULL, NULL, ega_write, NULL, NULL, ega); 18.17 + mem_mapping_set_addr(&ega->mapping, 0xa0000, 0x10000); 18.18 break; 18.19 case 0x8: /*32k at B0000*/ 18.20 - mem_sethandler(0xb0000, 0x08000, ega_read, NULL, NULL, ega_write, NULL, NULL, ega); 18.21 + mem_mapping_set_addr(&ega->mapping, 0xb0000, 0x08000); 18.22 break; 18.23 case 0xC: /*32k at B8000*/ 18.24 - mem_sethandler(0xb8000, 0x08000, ega_read, NULL, NULL, ega_write, NULL, NULL, ega); 18.25 + mem_mapping_set_addr(&ega->mapping, 0xb8000, 0x08000); 18.26 break; 18.27 } 18.28 break; 18.29 @@ -814,6 +813,7 @@ 18.30 18.31 ega_init(ega); 18.32 18.33 + mem_mapping_add(&ega->mapping, 0xa0000, 0x20000, ega_read, NULL, NULL, ega_write, NULL, NULL, ega); 18.34 timer_add(ega_poll, &ega->vidtime, TIMER_ALWAYS_ENABLED, ega); 18.35 io_sethandler(0x03a0, 0x0040, ega_in, NULL, NULL, ega_out, NULL, NULL, ega); 18.36 return ega;
19.1 --- a/src/vid_ega.h Sun Oct 13 16:33:43 2013 +0100 19.2 +++ b/src/vid_ega.h Sat Oct 19 17:06:55 2013 +0100 19.3 @@ -1,5 +1,7 @@ 19.4 typedef struct ega_t 19.5 { 19.6 + mem_mapping_t mapping; 19.7 + 19.8 uint8_t crtcreg; 19.9 uint8_t crtc[32]; 19.10 uint8_t gdcreg[16];
20.1 --- a/src/vid_et4000.c Sun Oct 13 16:33:43 2013 +0100 20.2 +++ b/src/vid_et4000.c Sat Oct 19 17:06:55 2013 +0100 20.3 @@ -3,6 +3,7 @@ 20.4 #include "ibm.h" 20.5 #include "device.h" 20.6 #include "io.h" 20.7 +#include "mem.h" 20.8 #include "video.h" 20.9 #include "vid_svga.h" 20.10 #include "vid_unk_ramdac.h"
21.1 --- a/src/vid_et4000w32.c Sun Oct 13 16:33:43 2013 +0100 21.2 +++ b/src/vid_et4000w32.c Sat Oct 19 17:06:55 2013 +0100 21.3 @@ -7,15 +7,18 @@ 21.4 #include "ibm.h" 21.5 #include "device.h" 21.6 #include "io.h" 21.7 +#include "mem.h" 21.8 #include "pci.h" 21.9 #include "video.h" 21.10 #include "vid_svga.h" 21.11 #include "vid_icd2061.h" 21.12 #include "vid_stg_ramdac.h" 21.13 -#include "mem.h" 21.14 21.15 typedef struct et4000w32p_t 21.16 { 21.17 + mem_mapping_t linear_mapping; 21.18 + mem_mapping_t mmu_mapping; 21.19 + 21.20 svga_t svga; 21.21 stg_ramdac_t ramdac; 21.22 icd2061_t icd2061; 21.23 @@ -258,12 +261,11 @@ 21.24 svga_t *svga = &et4000->svga; 21.25 21.26 pclog("recalcmapping %p\n", svga); 21.27 - mem_removehandler(et4000->linearbase_old, 0x200000, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); 21.28 - mem_removehandler( 0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 21.29 - mem_removehandler( 0xb0000, 0x10000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, et4000); 21.30 if (svga->crtc[0x36] & 0x10) /*Linear frame buffer*/ 21.31 { 21.32 - mem_sethandler(et4000->linearbase, 0x200000, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); 21.33 + mem_mapping_set_addr(&et4000->linear_mapping, et4000->linearbase, 0x200000); 21.34 + mem_mapping_disable(&svga->mapping); 21.35 + mem_mapping_disable(&et4000->mmu_mapping); 21.36 } 21.37 else 21.38 { 21.39 @@ -273,30 +275,36 @@ 21.40 switch (map) 21.41 { 21.42 case 0x0: case 0x4: case 0x8: case 0xC: /*128k at A0000*/ 21.43 - mem_sethandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 21.44 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000); 21.45 + mem_mapping_disable(&et4000->mmu_mapping); 21.46 break; 21.47 case 0x1: /*64k at A0000*/ 21.48 - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 21.49 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); 21.50 + mem_mapping_disable(&et4000->mmu_mapping); 21.51 break; 21.52 case 0x2: /*32k at B0000*/ 21.53 - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 21.54 + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); 21.55 + mem_mapping_disable(&et4000->mmu_mapping); 21.56 break; 21.57 case 0x3: /*32k at B8000*/ 21.58 - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 21.59 + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); 21.60 + mem_mapping_disable(&et4000->mmu_mapping); 21.61 break; 21.62 case 0x5: case 0x9: case 0xD: /*64k at A0000, MMU at B8000*/ 21.63 - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 21.64 - mem_sethandler(0xb8000, 0x08000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, et4000); 21.65 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); 21.66 + mem_mapping_set_addr(&et4000->mmu_mapping, 0xb8000, 0x08000); 21.67 break; 21.68 case 0x6: case 0xA: case 0xE: /*32k at B0000, MMU at A8000*/ 21.69 - mem_sethandler(0xa8000, 0x08000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, et4000); 21.70 - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 21.71 + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); 21.72 + mem_mapping_set_addr(&et4000->mmu_mapping, 0xa8000, 0x08000); 21.73 break; 21.74 case 0x7: case 0xB: case 0xF: /*32k at B8000, MMU at A8000*/ 21.75 - mem_sethandler(0xa8000, 0x08000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, et4000); 21.76 - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 21.77 + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); 21.78 + mem_mapping_set_addr(&et4000->mmu_mapping, 0xa8000, 0x08000); 21.79 break; 21.80 } 21.81 + 21.82 + mem_mapping_disable(&et4000->linear_mapping); 21.83 // pclog("ET4K map %02X\n", map); 21.84 } 21.85 et4000->linearbase_old = et4000->linearbase; 21.86 @@ -933,6 +941,9 @@ 21.87 et4000w32p_in, et4000w32p_out, 21.88 et4000w32p_hwcursor_draw); 21.89 21.90 + mem_mapping_add(&et4000->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &et4000->svga); 21.91 + mem_mapping_add(&et4000->mmu_mapping, 0, 0, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, et4000); 21.92 + 21.93 io_sethandler(0x03c0, 0x0020, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000); 21.94 21.95 io_sethandler(0x210A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
22.1 --- a/src/vid_hercules.c Sun Oct 13 16:33:43 2013 +0100 22.2 +++ b/src/vid_hercules.c Sat Oct 19 17:06:55 2013 +0100 22.3 @@ -9,6 +9,8 @@ 22.4 22.5 typedef struct hercules_t 22.6 { 22.7 + mem_mapping_t mapping; 22.8 + 22.9 uint8_t crtc[32]; 22.10 int crtcreg; 22.11 22.12 @@ -59,9 +61,10 @@ 22.13 return; 22.14 case 0x3bf: 22.15 hercules->ctrl2 = val; 22.16 - mem_removehandler(0xb8000, 0x08000, hercules_read, NULL, NULL, hercules_write, NULL, NULL, hercules); 22.17 if (val & 2) 22.18 - mem_sethandler(0xb8000, 0x08000, hercules_read, NULL, NULL, hercules_write, NULL, NULL, hercules); 22.19 + mem_mapping_set_addr(&hercules->mapping, 0xb0000, 0x10000); 22.20 + else 22.21 + mem_mapping_set_addr(&hercules->mapping, 0xb0000, 0x08000); 22.22 return; 22.23 } 22.24 } 22.25 @@ -308,7 +311,7 @@ 22.26 hercules->vram = malloc(0x10000); 22.27 22.28 timer_add(hercules_poll, &hercules->vidtime, TIMER_ALWAYS_ENABLED, hercules); 22.29 - mem_sethandler(0xb0000, 0x08000, hercules_read, NULL, NULL, hercules_write, NULL, NULL, hercules); 22.30 + mem_mapping_add(&hercules->mapping, 0xb0000, 0x08000, hercules_read, NULL, NULL, hercules_write, NULL, NULL, hercules); 22.31 io_sethandler(0x03b0, 0x0010, hercules_in, NULL, NULL, hercules_out, NULL, NULL, hercules); 22.32 22.33 for (c = 0; c < 256; c++)
23.1 --- a/src/vid_mda.c Sun Oct 13 16:33:43 2013 +0100 23.2 +++ b/src/vid_mda.c Sat Oct 19 17:06:55 2013 +0100 23.3 @@ -10,6 +10,8 @@ 23.4 23.5 typedef struct mda_t 23.6 { 23.7 + mem_mapping_t mapping; 23.8 + 23.9 uint8_t crtc[32]; 23.10 int crtcreg; 23.11 23.12 @@ -266,7 +268,7 @@ 23.13 mda->vram = malloc(0x1000); 23.14 23.15 timer_add(mda_poll, &mda->vidtime, TIMER_ALWAYS_ENABLED, mda); 23.16 - mem_sethandler(0xb0000, 0x08000, mda_read, NULL, NULL, mda_write, NULL, NULL, mda); 23.17 + mem_mapping_add(&mda->mapping, 0xb0000, 0x08000, mda_read, NULL, NULL, mda_write, NULL, NULL, mda); 23.18 io_sethandler(0x03b0, 0x0010, mda_in, NULL, NULL, mda_out, NULL, NULL, mda); 23.19 23.20 for (c = 0; c < 256; c++)
24.1 --- a/src/vid_olivetti_m24.c Sun Oct 13 16:33:43 2013 +0100 24.2 +++ b/src/vid_olivetti_m24.c Sat Oct 19 17:06:55 2013 +0100 24.3 @@ -11,6 +11,8 @@ 24.4 24.5 typedef struct m24_t 24.6 { 24.7 + mem_mapping_t mapping; 24.8 + 24.9 uint8_t crtc[32]; 24.10 int crtcreg; 24.11 24.12 @@ -457,7 +459,7 @@ 24.13 m24->vram = malloc(0x8000); 24.14 24.15 timer_add(m24_poll, &m24->vidtime, TIMER_ALWAYS_ENABLED, m24); 24.16 - mem_sethandler(0xb8000, 0x08000, m24_read, NULL, NULL, m24_write, NULL, NULL, m24); 24.17 + mem_mapping_add(&m24->mapping, 0xb8000, 0x08000, m24_read, NULL, NULL, m24_write, NULL, NULL, m24); 24.18 io_sethandler(0x03d0, 0x0010, m24_in, NULL, NULL, m24_out, NULL, NULL, m24); 24.19 return m24; 24.20 }
25.1 --- a/src/vid_oti067.c Sun Oct 13 16:33:43 2013 +0100 25.2 +++ b/src/vid_oti067.c Sat Oct 19 17:06:55 2013 +0100 25.3 @@ -3,6 +3,7 @@ 25.4 #include "ibm.h" 25.5 #include "device.h" 25.6 #include "io.h" 25.7 +#include "mem.h" 25.8 #include "video.h" 25.9 #include "vid_oti067.h" 25.10 #include "vid_svga.h"
26.1 --- a/src/vid_paradise.c Sun Oct 13 16:33:43 2013 +0100 26.2 +++ b/src/vid_paradise.c Sat Oct 19 17:06:55 2013 +0100 26.3 @@ -65,21 +65,20 @@ 26.4 { 26.5 if ((svga->gdcreg[6] & 0xc) != (val & 0xc)) 26.6 { 26.7 - mem_removehandler(0xa0000, 0x20000, paradise_read, NULL, NULL, paradise_write, NULL, NULL, paradise); 26.8 // pclog("Write mapping %02X\n", val); 26.9 switch (val&0xC) 26.10 { 26.11 case 0x0: /*128k at A0000*/ 26.12 - mem_sethandler(0xa0000, 0x20000, paradise_read, NULL, NULL, paradise_write, NULL, NULL, paradise); 26.13 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000); 26.14 break; 26.15 case 0x4: /*64k at A0000*/ 26.16 - mem_sethandler(0xa0000, 0x10000, paradise_read, NULL, NULL, paradise_write, NULL, NULL, paradise); 26.17 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); 26.18 break; 26.19 case 0x8: /*32k at B0000*/ 26.20 - mem_sethandler(0xb0000, 0x08000, paradise_read, NULL, NULL, paradise_write, NULL, NULL, paradise); 26.21 + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); 26.22 break; 26.23 case 0xC: /*32k at B8000*/ 26.24 - mem_sethandler(0xb8000, 0x08000, paradise_read, NULL, NULL, paradise_write, NULL, NULL, paradise); 26.25 + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); 26.26 break; 26.27 } 26.28 } 26.29 @@ -260,6 +259,9 @@ 26.30 paradise_in, paradise_out, 26.31 NULL); 26.32 26.33 + mem_mapping_set_handler(¶dise->svga.mapping, paradise_read, NULL, NULL, paradise_write, NULL, NULL); 26.34 + mem_mapping_set_p(¶dise->svga.mapping, paradise); 26.35 + 26.36 svga->crtc[0x31] = 'W'; 26.37 svga->crtc[0x32] = 'D'; 26.38 svga->crtc[0x33] = '9'; 26.39 @@ -287,6 +289,9 @@ 26.40 paradise_in, paradise_out, 26.41 NULL); 26.42 26.43 + mem_mapping_set_handler(¶dise->svga.mapping, paradise_read, NULL, NULL, paradise_write, NULL, NULL); 26.44 + mem_mapping_set_p(¶dise->svga.mapping, paradise); 26.45 + 26.46 svga->crtc[0x31] = 'W'; 26.47 svga->crtc[0x32] = 'D'; 26.48 svga->crtc[0x33] = '9';
27.1 --- a/src/vid_pc1512.c Sun Oct 13 16:33:43 2013 +0100 27.2 +++ b/src/vid_pc1512.c Sat Oct 19 17:06:55 2013 +0100 27.3 @@ -17,6 +17,8 @@ 27.4 27.5 typedef struct pc1512_t 27.6 { 27.7 + mem_mapping_t mapping; 27.8 + 27.9 uint8_t crtc[32]; 27.10 int crtcreg; 27.11 27.12 @@ -456,7 +458,7 @@ 27.13 pc1512->cgamode = 0x12; 27.14 27.15 timer_add(pc1512_poll, &pc1512->vidtime, TIMER_ALWAYS_ENABLED, pc1512); 27.16 - mem_sethandler(0xb8000, 0x08000, pc1512_read, NULL, NULL, pc1512_write, NULL, NULL, pc1512); 27.17 + mem_mapping_add(&pc1512->mapping, 0xb8000, 0x08000, pc1512_read, NULL, NULL, pc1512_write, NULL, NULL, pc1512); 27.18 io_sethandler(0x03d0, 0x0010, pc1512_in, NULL, NULL, pc1512_out, NULL, NULL, pc1512); 27.19 return pc1512; 27.20 }
28.1 --- a/src/vid_pc1640.c Sun Oct 13 16:33:43 2013 +0100 28.2 +++ b/src/vid_pc1640.c Sat Oct 19 17:06:55 2013 +0100 28.3 @@ -13,6 +13,9 @@ 28.4 28.5 typedef struct pc1640_t 28.6 { 28.7 + mem_mapping_t cga_mapping; 28.8 + mem_mapping_t ega_mapping; 28.9 + 28.10 cga_t cga; 28.11 ega_t ega; 28.12 28.13 @@ -28,25 +31,27 @@ 28.14 { 28.15 case 0x3db: 28.16 pc1640->cga_enabled = val & 0x40; 28.17 - mem_removehandler(0xa0000, 0x20000, ega_read, NULL, NULL, ega_write, NULL, NULL, &pc1640->ega); 28.18 - mem_removehandler(0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, &pc1640->cga); 28.19 if (pc1640->cga_enabled) 28.20 - mem_sethandler(0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, &pc1640->cga); 28.21 + { 28.22 + mem_mapping_enable(&pc1640->cga_mapping); 28.23 + mem_mapping_disable(&pc1640->ega_mapping); 28.24 + } 28.25 else 28.26 - { 28.27 + { 28.28 + mem_mapping_disable(&pc1640->cga_mapping); 28.29 switch (pc1640->ega.gdcreg[6] & 0xc) 28.30 { 28.31 case 0x0: /*128k at A0000*/ 28.32 - mem_sethandler(0xa0000, 0x20000, ega_read, NULL, NULL, ega_write, NULL, NULL, &pc1640->ega); 28.33 + mem_mapping_set_addr(&pc1640->ega_mapping, 0xa0000, 0x20000); 28.34 break; 28.35 case 0x4: /*64k at A0000*/ 28.36 - mem_sethandler(0xa0000, 0x10000, ega_read, NULL, NULL, ega_write, NULL, NULL, &pc1640->ega); 28.37 + mem_mapping_set_addr(&pc1640->ega_mapping, 0xa0000, 0x10000); 28.38 break; 28.39 case 0x8: /*32k at B0000*/ 28.40 - mem_sethandler(0xb0000, 0x08000, ega_read, NULL, NULL, ega_write, NULL, NULL, &pc1640->ega); 28.41 + mem_mapping_set_addr(&pc1640->ega_mapping, 0xb0000, 0x08000); 28.42 break; 28.43 case 0xC: /*32k at B8000*/ 28.44 - mem_sethandler(0xb8000, 0x08000, ega_read, NULL, NULL, ega_write, NULL, NULL, &pc1640->ega); 28.45 + mem_mapping_set_addr(&pc1640->ega_mapping, 0xb8000, 0x08000); 28.46 break; 28.47 } 28.48 } 28.49 @@ -115,7 +120,8 @@ 28.50 cga_init(&pc1640->cga); 28.51 28.52 timer_add(pc1640_poll, &pc1640->vidtime, TIMER_ALWAYS_ENABLED, pc1640); 28.53 - mem_sethandler(0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, cga); 28.54 + mem_mapping_add(&pc1640->cga_mapping, 0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, cga); 28.55 + mem_mapping_add(&pc1640->ega_mapping, 0, 0, ega_read, NULL, NULL, ega_write, NULL, NULL, ega); 28.56 io_sethandler(0x03a0, 0x0040, pc1640_in, NULL, NULL, pc1640_out, NULL, NULL, pc1640); 28.57 return cga; 28.58 }
29.1 --- a/src/vid_pc200.c Sun Oct 13 16:33:43 2013 +0100 29.2 +++ b/src/vid_pc200.c Sat Oct 19 17:06:55 2013 +0100 29.3 @@ -13,6 +13,8 @@ 29.4 29.5 typedef struct pc200_t 29.6 { 29.7 + mem_mapping_t mapping; 29.8 + 29.9 cga_t cga; 29.10 29.11 uint8_t reg_3dd, reg_3de, reg_3df; 29.12 @@ -109,7 +111,7 @@ 29.13 cga_init(&pc200->cga); 29.14 29.15 timer_add(cga_poll, &cga->vidtime, TIMER_ALWAYS_ENABLED, cga); 29.16 - mem_sethandler(0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, cga); 29.17 + mem_mapping_add(&pc200->mapping, 0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, cga); 29.18 io_sethandler(0x03d0, 0x0010, pc200_in, NULL, NULL, pc200_out, NULL, NULL, pc200); 29.19 return cga; 29.20 }
30.1 --- a/src/vid_s3.c Sun Oct 13 16:33:43 2013 +0100 30.2 +++ b/src/vid_s3.c Sat Oct 19 17:06:55 2013 +0100 30.3 @@ -13,6 +13,9 @@ 30.4 30.5 typedef struct s3_t 30.6 { 30.7 + mem_mapping_t linear_mapping; 30.8 + mem_mapping_t mmio_mapping; 30.9 + 30.10 svga_t svga; 30.11 sdac_ramdac_t ramdac; 30.12 30.13 @@ -239,7 +242,7 @@ 30.14 s3_t *s3 = (s3_t *)svga->p; 30.15 svga->hdisp = svga->hdisp_old; 30.16 30.17 - pclog("%i %i\n", svga->hdisp, svga->hdisp_time); 30.18 +// pclog("%i %i\n", svga->hdisp, svga->hdisp_time); 30.19 // pclog("recalctimings\n"); 30.20 svga->ma_latch |= (s3->ma_ext << 16); 30.21 // pclog("SVGA_MA %08X\n", svga_ma); 30.22 @@ -287,41 +290,38 @@ 30.23 } 30.24 30.25 // if (svga->bpp == 32) svga->hdisp *= 3; 30.26 - pclog("svga->hdisp %i %02X %i\n", svga->hdisp, svga->crtc[0x5d], svga->hdisp_time); 30.27 +// pclog("svga->hdisp %i %02X %i\n", svga->hdisp, svga->crtc[0x5d], svga->hdisp_time); 30.28 } 30.29 30.30 void s3_updatemapping(s3_t *s3) 30.31 { 30.32 svga_t *svga = &s3->svga; 30.33 30.34 - mem_removehandler(s3->linear_base, s3->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); 30.35 - 30.36 // video_write_a000_w = video_write_a000_l = NULL; 30.37 30.38 - mem_removehandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 30.39 30.40 - mem_removehandler(0xa0000, 0x10000, s3_accel_read, NULL, NULL, s3_accel_write, s3_accel_write_w, s3_accel_write_l, s3); 30.41 - 30.42 -// pclog("Update mapping - bank %02X ", gdcreg[6] & 0xc); 30.43 +// pclog("Update mapping - bank %02X ", svga->gdcreg[6] & 0xc); 30.44 switch (svga->gdcreg[6] & 0xc) /*Banked framebuffer*/ 30.45 { 30.46 case 0x0: /*128k at A0000*/ 30.47 - mem_sethandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 30.48 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000); 30.49 break; 30.50 case 0x4: /*64k at A0000*/ 30.51 - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 30.52 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); 30.53 break; 30.54 case 0x8: /*32k at B0000*/ 30.55 - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 30.56 + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); 30.57 break; 30.58 case 0xC: /*32k at B8000*/ 30.59 - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 30.60 + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); 30.61 break; 30.62 } 30.63 30.64 -// pclog("Linear framebuffer %02X ", crtc[0x58] & 0x10); 30.65 +// pclog("Linear framebuffer %02X ", svga->crtc[0x58] & 0x10); 30.66 if (svga->crtc[0x58] & 0x10) /*Linear framebuffer*/ 30.67 { 30.68 + mem_mapping_disable(&svga->mapping); 30.69 + 30.70 s3->linear_base = (svga->crtc[0x5a] << 16) | (svga->crtc[0x59] << 24); 30.71 switch (svga->crtc[0x58] & 3) 30.72 { 30.73 @@ -340,16 +340,24 @@ 30.74 } 30.75 s3->linear_base &= ~(s3->linear_size - 1); 30.76 // pclog("%08X %08X %02X %02X %02X\n", linear_base, linear_size, crtc[0x58], crtc[0x59], crtc[0x5a]); 30.77 -// pclog("Linear framebuffer at %08X size %08X\n", linear_base, linear_size); 30.78 +// pclog("Linear framebuffer at %08X size %08X\n", s3->linear_base, s3->linear_size); 30.79 if (s3->linear_base == 0xa0000) 30.80 - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 30.81 + { 30.82 + mem_mapping_disable(&s3->linear_mapping); 30.83 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); 30.84 +// mem_mapping_set_addr(&s3->linear_mapping, 0xa0000, 0x10000); 30.85 + } 30.86 else 30.87 - mem_sethandler(s3->linear_base, s3->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); 30.88 + mem_mapping_set_addr(&s3->linear_mapping, s3->linear_base, s3->linear_size); 30.89 } 30.90 + else 30.91 + mem_mapping_disable(&s3->linear_mapping); 30.92 30.93 -// pclog("Memory mapped IO %02X\n", crtc[0x53] & 0x10); 30.94 +// pclog("Memory mapped IO %02X\n", svga->crtc[0x53] & 0x10); 30.95 if (svga->crtc[0x53] & 0x10) /*Memory mapped IO*/ 30.96 - mem_sethandler(0xa0000, 0x10000, s3_accel_read, NULL, NULL, s3_accel_write, s3_accel_write_w, s3_accel_write_l, s3); 30.97 + mem_mapping_enable(&s3->mmio_mapping); 30.98 + else 30.99 + mem_mapping_disable(&s3->mmio_mapping); 30.100 } 30.101 30.102 30.103 @@ -1533,6 +1541,10 @@ 30.104 svga_t *svga = &s3->svga; 30.105 memset(s3, 0, sizeof(s3_t)); 30.106 30.107 + mem_mapping_add(&s3->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &s3->svga); 30.108 + mem_mapping_add(&s3->mmio_mapping, 0xa0000, 0x10000, s3_accel_read, NULL, NULL, s3_accel_write, s3_accel_write_w, s3_accel_write_l, s3); 30.109 + mem_mapping_disable(&s3->mmio_mapping); 30.110 + 30.111 svga_init(&s3->svga, s3, 1 << 22, /*4mb - 864 supports 8mb but buggy VESA driver reports 0mb*/ 30.112 s3_recalctimings, 30.113 s3_in, s3_out,
31.1 --- a/src/vid_s3_virge.c Sun Oct 13 16:33:43 2013 +0100 31.2 +++ b/src/vid_s3_virge.c Sat Oct 19 17:06:55 2013 +0100 31.3 @@ -15,6 +15,9 @@ 31.4 31.5 typedef struct virge_t 31.6 { 31.7 + mem_mapping_t linear_mapping; 31.8 + mem_mapping_t mmio_mapping; 31.9 + 31.10 svga_t svga; 31.11 31.12 uint8_t bank; 31.13 @@ -263,26 +266,20 @@ 31.14 { 31.15 svga_t *svga = &virge->svga; 31.16 31.17 - mem_removehandler(virge->linear_base, virge->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); 31.18 - 31.19 -// video_write_a000_w = video_write_a000_l = NULL; 31.20 - 31.21 - mem_removehandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 31.22 - mem_removehandler(0xa0000, 0x20000, s3_virge_mmio_read, s3_virge_mmio_read_w, s3_virge_mmio_read_l, s3_virge_mmio_write, s3_virge_mmio_write_w, s3_virge_mmio_write_l, virge); 31.23 pclog("Update mapping - bank %02X ", svga->gdcreg[6] & 0xc); 31.24 switch (svga->gdcreg[6] & 0xc) /*Banked framebuffer*/ 31.25 { 31.26 case 0x0: /*128k at A0000*/ 31.27 - mem_sethandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 31.28 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000); 31.29 break; 31.30 case 0x4: /*64k at A0000*/ 31.31 - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 31.32 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); 31.33 break; 31.34 case 0x8: /*32k at B0000*/ 31.35 - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 31.36 + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); 31.37 break; 31.38 case 0xC: /*32k at B8000*/ 31.39 - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 31.40 + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); 31.41 break; 31.42 } 31.43 31.44 @@ -309,20 +306,26 @@ 31.45 // pclog("%08X %08X %02X %02X %02X\n", linear_base, linear_size, crtc[0x58], crtc[0x59], crtc[0x5a]); 31.46 pclog("Linear framebuffer at %08X size %08X\n", virge->linear_base, virge->linear_size); 31.47 if (virge->linear_base == 0xa0000) 31.48 - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 31.49 + { 31.50 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); 31.51 + mem_mapping_disable(&virge->linear_mapping); 31.52 + } 31.53 else 31.54 - mem_sethandler(virge->linear_base, virge->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); 31.55 + mem_mapping_set_addr(&svga->mapping, virge->linear_base, virge->linear_size); 31.56 } 31.57 + else 31.58 + mem_mapping_disable(&virge->linear_mapping); 31.59 31.60 pclog("Memory mapped IO %02X\n", svga->crtc[0x53] & 0x18); 31.61 if ((svga->crtc[0x53] & 0x18) == 0x10) /*Memory mapped IO*/ 31.62 { 31.63 if (svga->crtc[0x53] & 0x20) 31.64 - mem_sethandler(0xb8000, 0x8000, s3_virge_mmio_read, s3_virge_mmio_read_w, s3_virge_mmio_read_l, s3_virge_mmio_write, s3_virge_mmio_write_w, s3_virge_mmio_write_l, virge); 31.65 + mem_mapping_set_addr(&virge->mmio_mapping, 0xb8000, 0x8000); 31.66 else 31.67 - mem_sethandler(0xa8000, 0x8000, s3_virge_mmio_read, s3_virge_mmio_read_w, s3_virge_mmio_read_l, s3_virge_mmio_write, s3_virge_mmio_write_w, s3_virge_mmio_write_l, virge); 31.68 + mem_mapping_set_addr(&virge->mmio_mapping, 0xa8000, 0x8000); 31.69 } 31.70 - 31.71 + else 31.72 + mem_mapping_disable(&virge->mmio_mapping); 31.73 } 31.74 31.75 31.76 @@ -451,6 +454,9 @@ 31.77 s3_virge_in, s3_virge_out, 31.78 s3_virge_hwcursor_draw); 31.79 31.80 + mem_mapping_add(&virge->mmio_mapping, 0, 0, s3_virge_mmio_read, s3_virge_mmio_read_w, s3_virge_mmio_read_l, s3_virge_mmio_write, s3_virge_mmio_write_w, s3_virge_mmio_write_l, virge); 31.81 + mem_mapping_add(&virge->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &virge->svga); 31.82 + 31.83 io_sethandler(0x03c0, 0x0020, s3_virge_in, NULL, NULL, s3_virge_out, NULL, NULL, virge); 31.84 31.85 virge->pci_regs[4] = 3;
32.1 --- a/src/vid_sdac_ramdac.c Sun Oct 13 16:33:43 2013 +0100 32.2 +++ b/src/vid_sdac_ramdac.c Sat Oct 19 17:06:55 2013 +0100 32.3 @@ -1,6 +1,7 @@ 32.4 /*87C716 'SDAC' true colour RAMDAC emulation*/ 32.5 /*Misidentifies as AT&T 21C504*/ 32.6 #include "ibm.h" 32.7 +#include "mem.h" 32.8 #include "video.h" 32.9 #include "vid_svga.h" 32.10 #include "vid_sdac_ramdac.h"
33.1 --- a/src/vid_stg_ramdac.c Sun Oct 13 16:33:43 2013 +0100 33.2 +++ b/src/vid_stg_ramdac.c Sat Oct 19 17:06:55 2013 +0100 33.3 @@ -1,5 +1,6 @@ 33.4 /*STG1702 true colour RAMDAC emulation*/ 33.5 #include "ibm.h" 33.6 +#include "mem.h" 33.7 #include "video.h" 33.8 #include "vid_svga.h" 33.9 #include "vid_stg_ramdac.h"
34.1 --- a/src/vid_svga.c Sun Oct 13 16:33:43 2013 +0100 34.2 +++ b/src/vid_svga.c Sat Oct 19 17:06:55 2013 +0100 34.3 @@ -139,21 +139,20 @@ 34.4 pclog("svga_out recalcmapping %p\n", svga); 34.5 if ((svga->gdcreg[6] & 0xc) != (val & 0xc)) 34.6 { 34.7 - mem_removehandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, p); 34.8 pclog("Write mapping %02X\n", val); 34.9 switch (val&0xC) 34.10 { 34.11 case 0x0: /*128k at A0000*/ 34.12 - mem_sethandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, p); 34.13 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000); 34.14 break; 34.15 case 0x4: /*64k at A0000*/ 34.16 - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, p); 34.17 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); 34.18 break; 34.19 case 0x8: /*32k at B0000*/ 34.20 - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, p); 34.21 + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); 34.22 break; 34.23 case 0xC: /*32k at B8000*/ 34.24 - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, p); 34.25 + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); 34.26 break; 34.27 } 34.28 } 34.29 @@ -641,7 +640,9 @@ 34.30 svga->video_out = video_out; 34.31 svga->hwcursor_draw = hwcursor_draw; 34.32 // _svga_recalctimings(svga); 34.33 - 34.34 + 34.35 + mem_mapping_add(&svga->mapping, 0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 34.36 + 34.37 timer_add(svga_poll, &svga->vidtime, TIMER_ALWAYS_ENABLED, svga); 34.38 vramp = svga->vram; 34.39 return 0; 34.40 @@ -1161,7 +1162,7 @@ 34.41 cycles -= video_timing_w; 34.42 cycles_lost += video_timing_w; 34.43 34.44 - if (svga_output) pclog("Writew %05X ", addr); 34.45 + if (svga_output) pclog("svga_writew: %05X ", addr); 34.46 addr = (addr & 0xffff) + svga->write_bank; 34.47 addr &= 0x7FFFFF; 34.48 if (addr >= svga->vram_limit) 34.49 @@ -1189,7 +1190,7 @@ 34.50 cycles -= video_timing_l; 34.51 cycles_lost += video_timing_l; 34.52 34.53 - if (svga_output) pclog("Writel %05X ", addr); 34.54 + if (svga_output) pclog("svga_writel: %05X ", addr); 34.55 addr = (addr & 0xffff) + svga->write_bank; 34.56 addr &= 0x7FFFFF; 34.57 if (addr >= svga->vram_limit)
35.1 --- a/src/vid_svga.h Sun Oct 13 16:33:43 2013 +0100 35.2 +++ b/src/vid_svga.h Sat Oct 19 17:06:55 2013 +0100 35.3 @@ -1,5 +1,7 @@ 35.4 typedef struct svga_t 35.5 { 35.6 + mem_mapping_t mapping; 35.7 + 35.8 uint8_t crtcreg; 35.9 uint8_t crtc[128]; 35.10 uint8_t gdcreg[16];
36.1 --- a/src/vid_svga_render.c Sun Oct 13 16:33:43 2013 +0100 36.2 +++ b/src/vid_svga_render.c Sat Oct 19 17:06:55 2013 +0100 36.3 @@ -1,4 +1,5 @@ 36.4 #include "ibm.h" 36.5 +#include "mem.h" 36.6 #include "video.h" 36.7 #include "vid_svga.h" 36.8 #include "vid_svga_render.h"
37.1 --- a/src/vid_tandy.c Sun Oct 13 16:33:43 2013 +0100 37.2 +++ b/src/vid_tandy.c Sat Oct 19 17:06:55 2013 +0100 37.3 @@ -12,6 +12,8 @@ 37.4 37.5 typedef struct tandy_t 37.6 { 37.7 + mem_mapping_t mapping; 37.8 + 37.9 uint8_t crtc[32]; 37.10 int crtcreg; 37.11 37.12 @@ -665,7 +667,7 @@ 37.13 q_filt[c] = 512.0 * sin((3.14 * (tandy_tint + c * 4) / 16.0) - 33.0 / 180.0); 37.14 } 37.15 timer_add(tandy_poll, &tandy->vidtime, TIMER_ALWAYS_ENABLED, tandy); 37.16 - mem_sethandler(0xb8000, 0x08000, tandy_read, NULL, NULL, tandy_write, NULL, NULL, tandy); 37.17 + mem_mapping_add(&tandy->mapping, 0xb8000, 0x08000, tandy_read, NULL, NULL, tandy_write, NULL, NULL, tandy); 37.18 io_sethandler(0x03d0, 0x0010, tandy_in, NULL, NULL, tandy_out, NULL, NULL, tandy); 37.19 io_sethandler(0x00a0, 0x0001, tandy_in, NULL, NULL, tandy_out, NULL, NULL, tandy); 37.20 return tandy;
38.1 --- a/src/vid_tkd8001_ramdac.c Sun Oct 13 16:33:43 2013 +0100 38.2 +++ b/src/vid_tkd8001_ramdac.c Sat Oct 19 17:06:55 2013 +0100 38.3 @@ -1,5 +1,6 @@ 38.4 /*Trident TKD8001 RAMDAC emulation*/ 38.5 #include "ibm.h" 38.6 +#include "mem.h" 38.7 #include "video.h" 38.8 #include "vid_svga.h" 38.9 #include "vid_tkd8001_ramdac.h"
39.1 --- a/src/vid_tvga.c Sun Oct 13 16:33:43 2013 +0100 39.2 +++ b/src/vid_tvga.c Sat Oct 19 17:06:55 2013 +0100 39.3 @@ -12,6 +12,9 @@ 39.4 39.5 typedef struct tvga_t 39.6 { 39.7 + mem_mapping_t linear_mapping; 39.8 + mem_mapping_t accel_mapping; 39.9 + 39.10 svga_t svga; 39.11 tkd8001_ramdac_t ramdac; 39.12 39.13 @@ -314,37 +317,37 @@ 39.14 { 39.15 svga_t *svga = &tvga->svga; 39.16 39.17 - pclog("tvga_recalcmapping : %02X %02X\n", svga->crtc[0x21], svga->gdcreg[6]); 39.18 - mem_removehandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 39.19 - mem_removehandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); 39.20 - mem_removehandler(0xbc000, 0x4000, tvga_accel_read, NULL, NULL, tvga_accel_write, NULL, NULL, tvga); 39.21 +// pclog("tvga_recalcmapping : %02X %02X\n", svga->crtc[0x21], svga->gdcreg[6]); 39.22 39.23 if (svga->crtc[0x21] & 0x20) 39.24 { 39.25 + mem_mapping_disable(&svga->mapping); 39.26 tvga->linear_base = ((svga->crtc[0x21] & 0xf) | ((svga->crtc[0x21] >> 2) & 0x30)) << 20; 39.27 tvga->linear_size = (svga->crtc[0x21] & 0x10) ? 0x200000 : 0x100000; 39.28 - mem_sethandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); 39.29 - pclog("Trident linear framebuffer at %08X - size %06X\n", tvga->linear_base, tvga->linear_size); 39.30 - mem_sethandler(0xbc000, 0x4000, tvga_accel_read, tvga_accel_read_w, tvga_accel_read_l, tvga_accel_write, tvga_accel_write_w, tvga_accel_write_l, tvga); 39.31 + mem_mapping_set_addr(&tvga->linear_mapping, tvga->linear_base, tvga->linear_size); 39.32 +// pclog("Trident linear framebuffer at %08X - size %06X\n", tvga->linear_base, tvga->linear_size); 39.33 + mem_mapping_enable(&tvga->accel_mapping); 39.34 } 39.35 else 39.36 { 39.37 // pclog("Write mapping %02X\n", val); 39.38 + mem_mapping_disable(&tvga->linear_mapping); 39.39 + mem_mapping_disable(&tvga->accel_mapping); 39.40 switch (svga->gdcreg[6] & 0xC) 39.41 { 39.42 case 0x0: /*128k at A0000*/ 39.43 - mem_sethandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 39.44 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000); 39.45 break; 39.46 case 0x4: /*64k at A0000*/ 39.47 - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 39.48 - mem_sethandler(0xbc000, 0x4000, tvga_accel_read, NULL, NULL, tvga_accel_write, NULL, NULL, tvga); 39.49 + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); 39.50 + mem_mapping_enable(&tvga->accel_mapping); 39.51 break; 39.52 case 0x8: /*32k at B0000*/ 39.53 - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 39.54 + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); 39.55 break; 39.56 case 0xC: /*32k at B8000*/ 39.57 - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); 39.58 - break; 39.59 + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); 39.60 + break; 39.61 } 39.62 } 39.63 } 39.64 @@ -385,6 +388,11 @@ 39.65 tvga_in, tvga_out, 39.66 NULL); 39.67 39.68 + mem_mapping_add(&tvga->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &tvga->svga); 39.69 + mem_mapping_add(&tvga->accel_mapping, 0xbc000, 0x4000, tvga_accel_read, tvga_accel_read_w, tvga_accel_read_l, tvga_accel_write, tvga_accel_write_w, tvga_accel_write_l, tvga); 39.70 + mem_mapping_disable(&tvga->linear_mapping); 39.71 + mem_mapping_disable(&tvga->accel_mapping); 39.72 + 39.73 io_sethandler(0x03c0, 0x0020, tvga_in, NULL, NULL, tvga_out, NULL, NULL, tvga); 39.74 39.75 return tvga; 39.76 @@ -399,6 +407,10 @@ 39.77 tvga_in, tvga_out, 39.78 tvga_hwcursor_draw); 39.79 39.80 + mem_mapping_add(&tvga->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &tvga->svga); 39.81 + mem_mapping_add(&tvga->accel_mapping, 0xbc000, 0x4000, tvga_accel_read, tvga_accel_read_w, tvga_accel_read_l, tvga_accel_write, tvga_accel_write_w, tvga_accel_write_l, tvga); 39.82 + mem_mapping_disable(&tvga->accel_mapping); 39.83 + 39.84 io_sethandler(0x03c0, 0x0020, tvga_in, NULL, NULL, tvga_out, NULL, NULL, tvga); 39.85 39.86 return tvga; 39.87 @@ -549,15 +561,15 @@ 39.88 } 39.89 } 39.90 } 39.91 - for (y = 0; y < 8; y++) 39.92 +/* for (y = 0; y < 8; y++) 39.93 { 39.94 if (count == -1) pclog("Pattern %i : %02X %02X %02X %02X %02X %02X %02X %02X\n", y, tvga->accel.tvga_pattern[y][0], tvga->accel.tvga_pattern[y][1], tvga->accel.tvga_pattern[y][2], tvga->accel.tvga_pattern[y][3], tvga->accel.tvga_pattern[y][4], tvga->accel.tvga_pattern[y][5], tvga->accel.tvga_pattern[y][6], tvga->accel.tvga_pattern[y][7]); 39.95 - } 39.96 - if (count == -1) pclog("Command %i %i\n", tvga->accel.command, TGUI_BITBLT); 39.97 - switch (tvga->accel.command) 39.98 + }*/ 39.99 +// if (count == -1) pclog("Command %i %i %p\n", tvga->accel.command, TGUI_BITBLT, tvga); 39.100 + switch (tvga->accel.command) 39.101 { 39.102 case TGUI_BITBLT: 39.103 - if (count == -1) pclog("BITBLT src %i,%i dst %i,%i size %i,%i flags %04X\n", tvga->accel.src_x, tvga->accel.src_y, tvga->accel.dst_x, tvga->accel.dst_y, tvga->accel.size_x, tvga->accel.size_y, tvga->accel.flags); 39.104 +// if (count == -1) pclog("BITBLT src %i,%i dst %i,%i size %i,%i flags %04X\n", tvga->accel.src_x, tvga->accel.src_y, tvga->accel.dst_x, tvga->accel.dst_y, tvga->accel.size_x, tvga->accel.size_y, tvga->accel.flags); 39.105 if (count == -1) 39.106 { 39.107 tvga->accel.src = tvga->accel.src_old = tvga->accel.src_x + (tvga->accel.src_y * tvga->accel.pitch); 39.108 @@ -571,17 +583,16 @@ 39.109 case TGUI_SRCCPU: 39.110 if (count == -1) 39.111 { 39.112 -// pclog("Blit start\n"); 39.113 +// pclog("Blit start TGUI_SRCCPU\n"); 39.114 if (svga->crtc[0x21] & 0x20) 39.115 - { 39.116 - mem_removehandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL); 39.117 - mem_sethandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, tvga_accel_write_fb_b, tvga_accel_write_fb_w, tvga_accel_write_fb_l, NULL); 39.118 - } 39.119 + mem_mapping_set_handler(&tvga->linear_mapping, svga_read_linear, svga_readw_linear, svga_readl_linear, tvga_accel_write_fb_b, tvga_accel_write_fb_w, tvga_accel_write_fb_l); 39.120 + 39.121 if (tvga->accel.use_src) 39.122 return; 39.123 } 39.124 else 39.125 count >>= 3; 39.126 +// pclog("TGUI_SRCCPU\n"); 39.127 while (count) 39.128 { 39.129 if (tvga->accel.bpp == 0) 39.130 @@ -628,8 +639,7 @@ 39.131 if (svga->crtc[0x21] & 0x20) 39.132 { 39.133 // pclog("Blit end\n"); 39.134 - mem_removehandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, tvga_accel_write_fb_b, tvga_accel_write_fb_w, tvga_accel_write_fb_l, NULL); 39.135 - mem_sethandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL); 39.136 + mem_mapping_set_handler(&tvga->linear_mapping, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear); 39.137 } 39.138 return; 39.139 } 39.140 @@ -643,12 +653,11 @@ 39.141 case TGUI_SRCMONO | TGUI_SRCCPU: 39.142 if (count == -1) 39.143 { 39.144 -// pclog("Blit start\n"); 39.145 +// pclog("Blit start TGUI_SRCMONO | TGUI_SRCCPU\n"); 39.146 if (svga->crtc[0x21] & 0x20) 39.147 - { 39.148 - mem_removehandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL); 39.149 - mem_sethandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, tvga_accel_write_fb_b, tvga_accel_write_fb_w, tvga_accel_write_fb_l, NULL); 39.150 - } 39.151 + mem_mapping_set_handler(&tvga->linear_mapping, svga_read_linear, svga_readw_linear, svga_readl_linear, tvga_accel_write_fb_b, tvga_accel_write_fb_w, tvga_accel_write_fb_l); 39.152 + 39.153 +// pclog(" %i\n", tvga->accel.command); 39.154 if (tvga->accel.use_src) 39.155 return; 39.156 } 39.157 @@ -691,8 +700,7 @@ 39.158 if (svga->crtc[0x21] & 0x20) 39.159 { 39.160 // pclog("Blit end\n"); 39.161 - mem_removehandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, tvga_accel_write_fb_b, tvga_accel_write_fb_w, tvga_accel_write_fb_l, NULL); 39.162 - mem_sethandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL); 39.163 + mem_mapping_set_handler(&tvga->linear_mapping, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear); 39.164 } 39.165 return; 39.166 } 39.167 @@ -748,7 +756,7 @@ 39.168 void tvga_accel_write(uint32_t addr, uint8_t val, void *p) 39.169 { 39.170 tvga_t *tvga = (tvga_t *)p; 39.171 - pclog("tvga_accel_write : %08X %02X %04X(%08X):%08X %02X\n", addr, val, CS,cs,pc, opcode); 39.172 +// pclog("tvga_accel_write : %08X %02X %04X(%08X):%08X %02X\n", addr, val, CS,cs,pc, opcode); 39.173 if ((addr & ~0xff) != 0xbff00) 39.174 return; 39.175 switch (addr & 0xff) 39.176 @@ -875,7 +883,7 @@ 39.177 void tvga_accel_write_w(uint32_t addr, uint16_t val, void *p) 39.178 { 39.179 tvga_t *tvga = (tvga_t *)p; 39.180 - pclog("tvga_accel_write_w %08X %04X\n", addr, val); 39.181 +// pclog("tvga_accel_write_w %08X %04X\n", addr, val); 39.182 tvga_accel_write(addr, val, tvga); 39.183 tvga_accel_write(addr + 1, val >> 8, tvga); 39.184 } 39.185 @@ -883,7 +891,7 @@ 39.186 void tvga_accel_write_l(uint32_t addr, uint32_t val, void *p) 39.187 { 39.188 tvga_t *tvga = (tvga_t *)p; 39.189 - pclog("tvga_accel_write_l %08X %08X\n", addr, val); 39.190 +// pclog("tvga_accel_write_l %08X %08X\n", addr, val); 39.191 tvga_accel_write(addr, val, tvga); 39.192 tvga_accel_write(addr + 1, val >> 8, tvga); 39.193 tvga_accel_write(addr + 2, val >> 16, tvga); 39.194 @@ -989,34 +997,37 @@ 39.195 uint16_t tvga_accel_read_w(uint32_t addr, void *p) 39.196 { 39.197 tvga_t *tvga = (tvga_t *)p; 39.198 - pclog("tvga_accel_read_w %08X\n", addr); 39.199 +// pclog("tvga_accel_read_w %08X\n", addr); 39.200 return tvga_accel_read(addr, tvga) | (tvga_accel_read(addr + 1, tvga) << 8); 39.201 } 39.202 39.203 uint32_t tvga_accel_read_l(uint32_t addr, void *p) 39.204 { 39.205 tvga_t *tvga = (tvga_t *)p; 39.206 - pclog("tvga_accel_read_l %08X\n", addr); 39.207 +// pclog("tvga_accel_read_l %08X\n", addr); 39.208 return tvga_accel_read_w(addr, tvga) | (tvga_accel_read_w(addr + 2, tvga) << 16); 39.209 } 39.210 39.211 void tvga_accel_write_fb_b(uint32_t addr, uint8_t val, void *p) 39.212 { 39.213 - tvga_t *tvga = (tvga_t *)p; 39.214 + svga_t *svga = (svga_t *)p; 39.215 + tvga_t *tvga = (tvga_t *)svga->p; 39.216 // pclog("tvga_accel_write_fb_b %08X %02X\n", addr, val); 39.217 tvga_accel_command(8, val << 24, tvga); 39.218 } 39.219 39.220 void tvga_accel_write_fb_w(uint32_t addr, uint16_t val, void *p) 39.221 { 39.222 - tvga_t *tvga = (tvga_t *)p; 39.223 + svga_t *svga = (svga_t *)p; 39.224 + tvga_t *tvga = (tvga_t *)svga->p; 39.225 // pclog("tvga_accel_write_fb_w %08X %04X\n", addr, val); 39.226 tvga_accel_command(16, (((val & 0xff00) >> 8) | ((val & 0x00ff) << 8)) << 16, tvga); 39.227 } 39.228 39.229 void tvga_accel_write_fb_l(uint32_t addr, uint32_t val, void *p) 39.230 { 39.231 - tvga_t *tvga = (tvga_t *)p; 39.232 + svga_t *svga = (svga_t *)p; 39.233 + tvga_t *tvga = (tvga_t *)svga->p; 39.234 // pclog("tvga_accel_write_fb_l %08X %08X\n", addr, val); 39.235 tvga_accel_command(32, ((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24), tvga); 39.236 }
40.1 --- a/src/vid_unk_ramdac.c Sun Oct 13 16:33:43 2013 +0100 40.2 +++ b/src/vid_unk_ramdac.c Sat Oct 19 17:06:55 2013 +0100 40.3 @@ -2,6 +2,7 @@ 40.4 It is possibly a Sierra 1502x 40.5 It's addressed by the TLIVESA1 driver for ET4000*/ 40.6 #include "ibm.h" 40.7 +#include "mem.h" 40.8 #include "video.h" 40.9 #include "vid_svga.h" 40.10 #include "vid_unk_ramdac.h"
41.1 --- a/src/vid_vga.c Sun Oct 13 16:33:43 2013 +0100 41.2 +++ b/src/vid_vga.c Sat Oct 19 17:06:55 2013 +0100 41.3 @@ -3,6 +3,7 @@ 41.4 #include "ibm.h" 41.5 #include "device.h" 41.6 #include "io.h" 41.7 +#include "mem.h" 41.8 #include "video.h" 41.9 #include "vid_svga.h" 41.10 #include "vid_vga.h"
42.1 --- a/src/vid_voodoo.c Sun Oct 13 16:33:43 2013 +0100 42.2 +++ b/src/vid_voodoo.c Sat Oct 19 17:06:55 2013 +0100 42.3 @@ -8,6 +8,10 @@ 42.4 42.5 static struct voodoo 42.6 { 42.7 + mem_mapping_t mmio_mapping; 42.8 + mem_mapping_t fb_mapping; 42.9 + mem_mapping_t tex_mapping; 42.10 + 42.11 int pci_enable; 42.12 42.13 uint32_t color0, color1; 42.14 @@ -669,18 +673,20 @@ 42.15 42.16 static void voodoo_recalcmapping() 42.17 { 42.18 - mem_removehandler(0x00000000, 0xffffffff, NULL, NULL, voodoo_readl, NULL, NULL, voodoo_writel, NULL); 42.19 - mem_removehandler(0x00000000, 0xffffffff, NULL, voodoo_fb_readw, voodoo_fb_readl, NULL, voodoo_fb_writew, voodoo_fb_writel, NULL); 42.20 - mem_removehandler(0x00000000, 0xffffffff, NULL, NULL, NULL, NULL, voodoo_tex_writew, voodoo_tex_writel, NULL); 42.21 if (voodoo.pci_enable) 42.22 { 42.23 pclog("voodoo_recalcmapping : memBaseAddr %08X\n", voodoo.memBaseAddr); 42.24 - mem_sethandler(voodoo.memBaseAddr, 0x003fffff, NULL, NULL, voodoo_readl, NULL, NULL, voodoo_writel, NULL); 42.25 - mem_sethandler(voodoo.memBaseAddr + 0x00400000, 0x003fffff, NULL, voodoo_fb_readw, voodoo_fb_readl, NULL, voodoo_fb_writew, voodoo_fb_writel, NULL); 42.26 - mem_sethandler(voodoo.memBaseAddr + 0x00800000, 0x007fffff, NULL, NULL, NULL, NULL, voodoo_tex_writew, voodoo_tex_writel, NULL); 42.27 + mem_mapping_set_addr(&voodoo.mmio_mapping, voodoo.memBaseAddr, 0x00400000); 42.28 + mem_mapping_set_addr(&voodoo.fb_mapping, voodoo.memBaseAddr + 0x00400000, 0x00400000); 42.29 + mem_mapping_set_addr(&voodoo.tex_mapping, voodoo.memBaseAddr + 0x00800000, 0x00800000); 42.30 } 42.31 else 42.32 + { 42.33 pclog("voodoo_recalcmapping : disabled\n"); 42.34 + mem_mapping_disable(&voodoo.mmio_mapping); 42.35 + mem_mapping_disable(&voodoo.fb_mapping); 42.36 + mem_mapping_disable(&voodoo.tex_mapping); 42.37 + } 42.38 } 42.39 42.40 uint8_t voodoo_pci_read(int func, int addr, void *priv) 42.41 @@ -727,6 +733,11 @@ 42.42 return; 42.43 voodoo_make_dither(); 42.44 pci_add(voodoo_pci_read, voodoo_pci_write, NULL); 42.45 + 42.46 + mem_mapping_add(&voodoo.mmio_mapping, 0, 0, NULL, NULL, voodoo_readl, NULL, NULL, voodoo_writel, NULL); 42.47 + mem_mapping_add(&voodoo.fb_mapping, 0, 0, NULL, voodoo_fb_readw, voodoo_fb_readl, NULL, voodoo_fb_writew, voodoo_fb_writel, NULL); 42.48 + mem_mapping_add(&voodoo.tex_mapping, 0, 0, NULL, NULL, NULL, NULL, voodoo_tex_writew, voodoo_tex_writel, NULL); 42.49 + 42.50 voodoo.fb_mem = malloc(2 * 1024 * 1024); 42.51 voodoo.tex_mem = malloc(2 * 1024 * 1024); 42.52 }