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view src/x86_ops_mmx_mov.h @ 142:bd46c39a78e8

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Implemented selector limits on some instructions - fixes LBA2. GPFs in real mode now work. Selectors correctly zeroed on far return to lower privilege.
author TomW
date Wed Aug 13 20:33:56 2014 +0100
parents cdce787defd5
children
line source
1 int opMOVD_l_mm_a16(uint32_t fetchdat)
2 {
3 MMX_ENTER();
4
5 fetch_ea_16(fetchdat);
6 if (mod == 3)
7 {
8 MM[reg].l[0] = regs[rm].l;
9 MM[reg].l[1] = 0;
10 cycles--;
11 }
12 else
13 {
14 uint32_t dst;
15
16 dst = readmeml(easeg, eaaddr); if (abrt) return 0;
17 MM[reg].l[0] = dst;
18 MM[reg].l[1] = 0;
19
20 cycles -= 2;
21 }
22 return 0;
23 }
24 int opMOVD_l_mm_a32(uint32_t fetchdat)
25 {
26 MMX_ENTER();
27
28 fetch_ea_32(fetchdat);
29 if (mod == 3)
30 {
31 MM[reg].l[0] = regs[rm].l;
32 MM[reg].l[1] = 0;
33 cycles--;
34 }
35 else
36 {
37 uint32_t dst;
38
39 dst = readmeml(easeg, eaaddr); if (abrt) return 0;
40 MM[reg].l[0] = dst;
41 MM[reg].l[1] = 0;
42
43 cycles -= 2;
44 }
45 return 0;
46 }
47
48 int opMOVD_mm_l_a16(uint32_t fetchdat)
49 {
50 MMX_ENTER();
51
52 fetch_ea_16(fetchdat);
53 if (mod == 3)
54 {
55 regs[rm].l = MM[reg].l[0];
56 cycles--;
57 }
58 else
59 {
60 CHECK_WRITE(ea_seg, eaaddr, eaaddr + 3);
61 writememl(easeg, eaaddr, MM[reg].l[0]); if (abrt) return 0;
62 cycles -= 2;
63 }
64 return 0;
65 }
66 int opMOVD_mm_l_a32(uint32_t fetchdat)
67 {
68 MMX_ENTER();
69
70 fetch_ea_32(fetchdat);
71 if (mod == 3)
72 {
73 regs[rm].l = MM[reg].l[0];
74 cycles--;
75 }
76 else
77 {
78 CHECK_WRITE(ea_seg, eaaddr, eaaddr + 3);
79 writememl(easeg, eaaddr, MM[reg].l[0]); if (abrt) return 0;
80 cycles -= 2;
81 }
82 return 0;
83 }
84
85 int opMOVQ_q_mm_a16(uint32_t fetchdat)
86 {
87 MMX_ENTER();
88
89 fetch_ea_16(fetchdat);
90 if (mod == 3)
91 {
92 MM[reg].q = MM[rm].q;
93 cycles--;
94 }
95 else
96 {
97 uint32_t dst[2];
98
99 dst[0] = readmeml(easeg, eaaddr);
100 dst[1] = readmeml(easeg, eaaddr + 4); if (abrt) return 0;
101 MM[reg].l[0] = dst[0];
102 MM[reg].l[1] = dst[1];
103 cycles -= 2;
104 }
105 return 0;
106 }
107 int opMOVQ_q_mm_a32(uint32_t fetchdat)
108 {
109 MMX_ENTER();
110
111 fetch_ea_32(fetchdat);
112 if (mod == 3)
113 {
114 MM[reg].q = MM[rm].q;
115 cycles--;
116 }
117 else
118 {
119 uint32_t dst[2];
120
121 dst[0] = readmeml(easeg, eaaddr);
122 dst[1] = readmeml(easeg, eaaddr + 4); if (abrt) return 0;
123 MM[reg].l[0] = dst[0];
124 MM[reg].l[1] = dst[1];
125 cycles -= 2;
126 }
127 return 0;
128 }
129
130 int opMOVQ_mm_q_a16(uint32_t fetchdat)
131 {
132 MMX_ENTER();
133
134 fetch_ea_16(fetchdat);
135 if (mod == 3)
136 {
137 MM[rm].q = MM[reg].q;
138 cycles--;
139 }
140 else
141 {
142 CHECK_WRITE(ea_seg, eaaddr, eaaddr + 7);
143 writememl(easeg, eaaddr, MM[reg].l[0]);
144 writememl(easeg, eaaddr + 4, MM[reg].l[1]); if (abrt) return 0;
145 cycles -= 2;
146 }
147 return 0;
148 }
149 int opMOVQ_mm_q_a32(uint32_t fetchdat)
150 {
151 MMX_ENTER();
152
153 fetch_ea_32(fetchdat);
154 if (mod == 3)
155 {
156 MM[rm].q = MM[reg].q;
157 cycles--;
158 }
159 else
160 {
161 CHECK_WRITE(ea_seg, eaaddr, eaaddr + 7);
162 writememl(easeg, eaaddr, MM[reg].l[0]);
163 writememl(easeg, eaaddr + 4, MM[reg].l[1]); if (abrt) return 0;
164 cycles -= 2;
165 }
166 return 0;
167 }