PCem

view src/x86_ops_mov_ctrl.h @ 150:871b132c6158

find changesets by author, revision, files, or words in the commit message
Implemented CR4 register for Winchip. Currently only Time Stamp Disable (TSD) has an effect. Fixed stupid bug in WRMSR - MSRs can now be written with values other than zero.
author TomW
date Sat Aug 23 16:28:16 2014 +0100
parents c49302f432e2
children
line source
1 static int opMOV_r_CRx_a16(uint32_t fetchdat)
2 {
3 if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
4 {
5 pclog("Can't load from CRx\n");
6 x86gpf(NULL, 0);
7 return 0;
8 }
9 fetch_ea_16(fetchdat);
10 switch (reg)
11 {
12 case 0:
13 regs[rm].l = cr0;
14 if (is486) regs[rm].l |= 0x10; /*ET hardwired on 486*/
15 break;
16 case 2:
17 regs[rm].l = cr2;
18 break;
19 case 3:
20 regs[rm].l = cr3;
21 break;
22 case 4:
23 if (cpu_hasCR4)
24 {
25 regs[rm].l = cr4;
26 break;
27 }
28 default:
29 pclog("Bad read of CR%i %i\n",rmdat&7,reg);
30 pc = oldpc;
31 x86illegal();
32 break;
33 }
34 cycles -= 6;
35 return 0;
36 }
37 static int opMOV_r_CRx_a32(uint32_t fetchdat)
38 {
39 if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
40 {
41 pclog("Can't load from CRx\n");
42 x86gpf(NULL, 0);
43 return 0;
44 }
45 fetch_ea_32(fetchdat);
46 switch (reg)
47 {
48 case 0:
49 regs[rm].l = cr0;
50 if (is486) regs[rm].l |= 0x10; /*ET hardwired on 486*/
51 break;
52 case 2:
53 regs[rm].l = cr2;
54 break;
55 case 3:
56 regs[rm].l = cr3;
57 break;
58 case 4:
59 if (cpu_hasCR4)
60 {
61 regs[rm].l = cr4;
62 break;
63 }
64 default:
65 pclog("Bad read of CR%i %i\n",rmdat&7,reg);
66 pc = oldpc;
67 x86illegal();
68 break;
69 }
70 cycles -= 6;
71 return 0;
72 }
73
74 static int opMOV_r_DRx_a16(uint32_t fetchdat)
75 {
76 if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
77 {
78 pclog("Can't load from DRx\n");
79 x86gpf(NULL, 0);
80 return 0;
81 }
82 fetch_ea_16(fetchdat);
83 regs[rm].l = 0;
84 cycles -= 6;
85 return 0;
86 }
87 static int opMOV_r_DRx_a32(uint32_t fetchdat)
88 {
89 if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
90 {
91 pclog("Can't load from DRx\n");
92 x86gpf(NULL, 0);
93 return 0;
94 }
95 fetch_ea_32(fetchdat);
96 regs[rm].l = 0;
97 cycles -= 6;
98 return 0;
99 }
100
101 static int opMOV_CRx_r_a16(uint32_t fetchdat)
102 {
103 if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
104 {
105 pclog("Can't load CRx\n");
106 x86gpf(NULL,0);
107 return 0;
108 }
109 fetch_ea_16(fetchdat);
110 switch (reg)
111 {
112 case 0:
113 if ((regs[rm].l ^ cr0) & 0x80000001) flushmmucache();
114 cr0 = regs[rm].l;
115 if (cpu_16bitbus) cr0 |= 0x10;
116 if (!(cr0 & 0x80000000)) mmu_perm=4;
117 break;
118 case 2:
119 cr2 = regs[rm].l;
120 break;
121 case 3:
122 cr3 = regs[rm].l;
123 flushmmucache();
124 break;
125 case 4:
126 if (cpu_hasCR4)
127 {
128 cr4 = regs[rm].l & cpu_CR4_mask;
129 break;
130 }
131
132 default:
133 pclog("Bad load CR%i\n", reg);
134 pc = oldpc;
135 x86illegal();
136 break;
137 }
138 cycles -= 10;
139 return 0;
140 }
141 static int opMOV_CRx_r_a32(uint32_t fetchdat)
142 {
143 if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
144 {
145 pclog("Can't load CRx\n");
146 x86gpf(NULL,0);
147 return 0;
148 }
149 fetch_ea_32(fetchdat);
150 switch (reg)
151 {
152 case 0:
153 if ((regs[rm].l ^ cr0) & 0x80000001) flushmmucache();
154 cr0 = regs[rm].l;
155 if (cpu_16bitbus) cr0 |= 0x10;
156 if (!(cr0 & 0x80000000)) mmu_perm=4;
157 break;
158 case 2:
159 cr2 = regs[rm].l;
160 break;
161 case 3:
162 cr3 = regs[rm].l;
163 flushmmucache();
164 break;
165 case 4:
166 if (cpu_hasCR4)
167 {
168 cr4 = regs[rm].l & cpu_CR4_mask;
169 break;
170 }
171
172 default:
173 pclog("Bad load CR%i\n", reg);
174 pc = oldpc;
175 x86illegal();
176 break;
177 }
178 cycles -= 10;
179 return 0;
180 }
181
182 static int opMOV_DRx_r_a16(uint32_t fetchdat)
183 {
184 if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
185 {
186 pclog("Can't load DRx\n");
187 x86gpf(NULL, 0);
188 return 0;
189 }
190 fetch_ea_16(fetchdat);
191 cycles -= 6;
192 return 0;
193 }
194 static int opMOV_DRx_r_a32(uint32_t fetchdat)
195 {
196 if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
197 {
198 pclog("Can't load DRx\n");
199 x86gpf(NULL, 0);
200 return 0;
201 }
202 fetch_ea_16(fetchdat);
203 cycles -= 6;
204 return 0;
205 }
206
207 static int opMOV_r_TRx_a16(uint32_t fetchdat)
208 {
209 if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
210 {
211 pclog("Can't load from TRx\n");
212 x86gpf(NULL, 0);
213 return 0;
214 }
215 fetch_ea_16(fetchdat);
216 regs[rm].l = 0;
217 cycles -= 6;
218 return 0;
219 }
220 static int opMOV_r_TRx_a32(uint32_t fetchdat)
221 {
222 if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
223 {
224 pclog("Can't load from TRx\n");
225 x86gpf(NULL, 0);
226 return 0;
227 }
228 fetch_ea_32(fetchdat);
229 regs[rm].l = 0;
230 cycles -= 6;
231 return 0;
232 }
233
234 static int opMOV_TRx_r_a16(uint32_t fetchdat)
235 {
236 if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
237 {
238 pclog("Can't load TRx\n");
239 x86gpf(NULL, 0);
240 return 0;
241 }
242 fetch_ea_16(fetchdat);
243 cycles -= 6;
244 return 0;
245 }
246 static int opMOV_TRx_r_a32(uint32_t fetchdat)
247 {
248 if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
249 {
250 pclog("Can't load TRx\n");
251 x86gpf(NULL, 0);
252 return 0;
253 }
254 fetch_ea_16(fetchdat);
255 cycles -= 6;
256 return 0;
257 }
258