PCem
view src/ibm.h @ 150:871b132c6158
Implemented CR4 register for Winchip. Currently only Time Stamp Disable (TSD) has an effect.
Fixed stupid bug in WRMSR - MSRs can now be written with values other than zero.
| author | TomW |
|---|---|
| date | Sat Aug 23 16:28:16 2014 +0100 |
| parents | bd46c39a78e8 |
| children | 55564c65aa15 |
line source
1 #include <stdio.h>
2 #include <stdint.h>
3 #include <string.h>
4 #define printf pclog
6 /*Memory*/
7 uint8_t *ram,*vram;
9 uint32_t rammask;
11 int readlookup[256],readlookupp[256];
12 uint32_t *readlookup2;
13 int readlnext;
14 int writelookup[256],writelookupp[256];
15 uint32_t *writelookup2;
16 int writelnext;
18 extern int mmu_perm;
20 #define readmemb(a) ((readlookup2[(a)>>12]==0xFFFFFFFF)?readmembl(a):*(uint8_t *)(readlookup2[(a) >> 12] + (a)))
21 #define readmemw(s,a) ((readlookup2[((s)+(a))>>12]==0xFFFFFFFF || (s)==0xFFFFFFFF || (((s)+(a))&0xFFF)>0xFFE)?readmemwl(s,a):*(uint16_t *)(readlookup2[((s)+(a))>>12]+(s)+(a)))
22 #define readmeml(s,a) ((readlookup2[((s)+(a))>>12]==0xFFFFFFFF || (s)==0xFFFFFFFF || (((s)+(a))&0xFFF)>0xFFC)?readmemll(s,a):*(uint32_t *)(readlookup2[((s)+(a))>>12]+(s)+(a)))
24 //#define writememb(a,v) if (writelookup2[(a)>>12]==0xFFFFFFFF) writemembl(a,v); else ram[writelookup2[(a)>>12]+((a)&0xFFF)]=v
25 //#define writememw(s,a,v) if (writelookup2[((s)+(a))>>12]==0xFFFFFFFF || (s)==0xFFFFFFFF) writememwl(s,a,v); else *((uint16_t *)(&ram[writelookup2[((s)+(a))>>12]+(((s)+(a))&0xFFF)]))=v
26 //#define writememl(s,a,v) if (writelookup2[((s)+(a))>>12]==0xFFFFFFFF || (s)==0xFFFFFFFF) writememll(s,a,v); else *((uint32_t *)(&ram[writelookup2[((s)+(a))>>12]+(((s)+(a))&0xFFF)]))=v
27 //#define readmemb(a) ((isram[((a)>>16)&255] && !(cr0>>31))?ram[a&0xFFFFFF]:readmembl(a))
28 //#define writememb(a,v) if (isram[((a)>>16)&255] && !(cr0>>31)) ram[a&0xFFFFFF]=v; else writemembl(a,v)
30 //void writememb(uint32_t addr, uint8_t val);
31 uint8_t readmembl(uint32_t addr);
32 void writemembl(uint32_t addr, uint8_t val);
33 uint8_t readmemb386l(uint32_t seg, uint32_t addr);
34 void writememb386l(uint32_t seg, uint32_t addr, uint8_t val);
35 uint16_t readmemwl(uint32_t seg, uint32_t addr);
36 void writememwl(uint32_t seg, uint32_t addr, uint16_t val);
37 uint32_t readmemll(uint32_t seg, uint32_t addr);
38 void writememll(uint32_t seg, uint32_t addr, uint32_t val);
40 uint8_t *getpccache(uint32_t a);
42 uint32_t mmutranslatereal(uint32_t addr, int rw);
44 void addreadlookup(uint32_t virt, uint32_t phys);
45 void addwritelookup(uint32_t virt, uint32_t phys);
48 /*IO*/
49 uint8_t inb(uint16_t port);
50 void outb(uint16_t port, uint8_t val);
51 uint16_t inw(uint16_t port);
52 void outw(uint16_t port, uint16_t val);
53 uint32_t inl(uint16_t port);
54 void outl(uint16_t port, uint32_t val);
56 FILE *romfopen(char *fn, char *mode);
57 extern int shadowbios,shadowbios_write;
58 extern int cache;
59 extern int mem_size;
60 extern int readlnum,writelnum;
61 extern int memwaitstate;
64 /*Processor*/
65 #define EAX regs[0].l
66 #define ECX regs[1].l
67 #define EDX regs[2].l
68 #define EBX regs[3].l
69 #define ESP regs[4].l
70 #define EBP regs[5].l
71 #define ESI regs[6].l
72 #define EDI regs[7].l
73 #define AX regs[0].w
74 #define CX regs[1].w
75 #define DX regs[2].w
76 #define BX regs[3].w
77 #define SP regs[4].w
78 #define BP regs[5].w
79 #define SI regs[6].w
80 #define DI regs[7].w
81 #define AL regs[0].b.l
82 #define AH regs[0].b.h
83 #define CL regs[1].b.l
84 #define CH regs[1].b.h
85 #define DL regs[2].b.l
86 #define DH regs[2].b.h
87 #define BL regs[3].b.l
88 #define BH regs[3].b.h
90 typedef union
91 {
92 uint32_t l;
93 uint16_t w;
94 struct
95 {
96 uint8_t l,h;
97 } b;
98 } x86reg;
100 x86reg regs[8];
101 uint16_t flags,eflags;
102 uint32_t /*cs,ds,es,ss,*/oldds,oldss,pc,olddslimit,oldsslimit,olddslimitw,oldsslimitw;
103 //uint16_t msw;
105 extern int ins,output;
106 extern int cycdiff;
108 typedef struct
109 {
110 uint32_t base;
111 uint32_t limit;
112 uint8_t access;
113 uint16_t seg;
114 uint32_t limit_low, limit_high;
115 } x86seg;
117 x86seg gdt,ldt,idt,tr;
118 x86seg _cs,_ds,_es,_ss,_fs,_gs;
119 x86seg _oldds;
121 extern x86seg *ea_seg;
123 uint32_t pccache;
124 uint8_t *pccache2;
125 /*Segments -
126 _cs,_ds,_es,_ss are the segment structures
127 CS,DS,ES,SS is the 16-bit data
128 cs,ds,es,ss are defines to the bases*/
129 //uint16_t CS,DS,ES,SS;
130 #define CS _cs.seg
131 #define DS _ds.seg
132 #define ES _es.seg
133 #define SS _ss.seg
134 #define FS _fs.seg
135 #define GS _gs.seg
136 #define cs _cs.base
137 #define ds _ds.base
138 #define es _es.base
139 #define ss _ss.base
140 #define fs _fs.base
141 #define gs _gs.base
143 #define CPL ((_cs.access>>5)&3)
145 void loadseg(uint16_t seg, x86seg *s);
146 void loadcs(uint16_t seg);
148 union
149 {
150 uint32_t l;
151 uint16_t w;
152 } CR0;
154 #define cr0 CR0.l
155 #define msw CR0.w
157 uint32_t cr2, cr3, cr4;
159 #define C_FLAG 0x0001
160 #define P_FLAG 0x0004
161 #define A_FLAG 0x0010
162 #define Z_FLAG 0x0040
163 #define N_FLAG 0x0080
164 #define T_FLAG 0x0100
165 #define I_FLAG 0x0200
166 #define D_FLAG 0x0400
167 #define V_FLAG 0x0800
168 #define NT_FLAG 0x4000
169 #define VM_FLAG 0x0002 /*In EFLAGS*/
171 #define WP_FLAG 0x10000 /*In CR0*/
173 #define IOPL ((flags>>12)&3)
175 #define IOPLp ((!(msw&1)) || (CPL<=IOPL))
176 //#define IOPLp 1
178 //#define IOPLV86 ((!(msw&1)) || (CPL<=IOPL))
179 extern int cycles;
180 extern int cycles_lost;
181 extern int is486;
182 extern uint8_t opcode;
183 extern int insc;
184 extern int fpucount;
185 extern float mips,flops;
186 extern int clockrate;
187 extern int cgate16;
188 extern int CPUID;
190 extern int cpl_override;
192 /*Timer*/
193 typedef struct PIT
194 {
195 uint32_t l[3];
196 int c[3];
197 uint8_t m[3];
198 uint8_t ctrl,ctrls[2];
199 int wp,rm[3],wm[3];
200 uint16_t rl[3];
201 int thit[3];
202 int delay[3];
203 int rereadlatch[3];
204 int gate[3];
205 int out[3];
206 int running[3];
207 int enabled[3];
208 int newcount[3];
209 int count[3];
210 int using_timer[3];
211 int initial[3];
212 } PIT;
214 PIT pit;
215 void setpitclock(float clock);
216 int pitcount;
218 float pit_timer0_freq();
222 /*DMA*/
223 typedef struct DMA
224 {
225 uint16_t ab[4],ac[4];
226 uint16_t cb[4];
227 int cc[4];
228 int wp;
229 uint8_t m,mode[4];
230 uint8_t page[4];
231 uint8_t stat;
232 uint8_t command;
233 } DMA;
235 DMA dma,dma16;
238 /*PPI*/
239 typedef struct PPI
240 {
241 int s2;
242 uint8_t pa,pb;
243 } PPI;
245 PPI ppi;
246 extern int key_inhibit;
249 /*PIC*/
250 typedef struct PIC
251 {
252 uint8_t icw1,mask,ins,pend,mask2;
253 int icw;
254 uint8_t vector;
255 int read;
256 } PIC;
258 PIC pic,pic2;
259 extern int pic_intpending;
260 int intcount;
263 int disctime;
264 char discfns[2][256];
265 int driveempty[2];
268 /*Config stuff*/
269 #define MDA ((gfxcard==GFX_MDA || gfxcard==GFX_HERCULES) && (romset<ROM_TANDY || romset>=ROM_IBMAT))
270 #define HERCULES (gfxcard==GFX_HERCULES && (romset<ROM_TANDY || romset>=ROM_IBMAT))
271 #define AMSTRAD (romset==ROM_PC1512 || romset==ROM_PC1640 || romset==ROM_PC3086)
272 #define AMSTRADIO (romset==ROM_PC1512 || romset==ROM_PC1640 || romset==ROM_PC200 || romset==ROM_PC2086 || romset == ROM_PC3086)
273 #define TANDY (romset==ROM_TANDY/* || romset==ROM_IBMPCJR*/)
274 #define VID_EGA (gfxcard==GFX_EGA)
275 #define EGA (romset==ROM_PC1640 || VID_EGA || VGA)
276 #define VGA ((gfxcard>=GFX_TVGA || romset==ROM_ACER386) && romset!=ROM_PC1640 && romset!=ROM_PC1512 && romset!=ROM_TANDY && romset!=ROM_PC200)
277 #define SVGA (gfxcard==GFX_ET4000 && VGA)
278 #define TRIDENT (gfxcard==GFX_TVGA && !OTI067)
279 #define OTI067 (romset==ROM_ACER386)
280 #define ET4000 (gfxcard==GFX_ET4000 && VGA)
281 #define ET4000W32 (gfxcard==GFX_ET4000W32 && VGA)
282 #define AT (romset>=ROM_IBMAT)
283 #define PCI (romset >= ROM_PCI486)
284 #define PCJR (romset == ROM_IBMPCJR)
286 #define AMIBIOS (romset==ROM_AMI386 || romset==ROM_AMI486 || romset == ROM_WIN486)
288 int GAMEBLASTER, GUS, SSI2001;
290 enum
291 {
292 ROM_IBMPC = 0, /*301 keyboard error, 131 cassette (!!!) error*/
293 ROM_IBMXT, /*301 keyboard error*/
294 ROM_IBMPCJR,
295 ROM_GENXT, /*'Generic XT BIOS'*/
296 ROM_DTKXT,
297 ROM_EUROPC,
298 ROM_OLIM24,
299 ROM_TANDY,
300 ROM_PC1512,
301 ROM_PC200,
302 ROM_PC1640,
303 ROM_PC2086,
304 ROM_PC3086,
305 ROM_IBMAT,
306 ROM_CMDPC30,
307 ROM_AMI286,
308 ROM_DELL200,
309 ROM_MISC286,
310 ROM_IBMAT386,
311 ROM_ACER386,
312 ROM_MEGAPC,
313 ROM_AMI386,
314 ROM_AMI486,
315 ROM_WIN486,
316 ROM_PCI486,
317 ROM_SIS496,
318 ROM_430VX,
320 ROM_MAX
321 };
323 extern int romspresent[ROM_MAX];
325 //#define ROM_IBMPCJR 5 /*Not working! ROMs are corrupt*/
326 #define is386 (romset>=ROM_IBMAT386)
327 #define is386sx 0
329 int hasfpu;
330 int romset;
332 enum
333 {
334 GFX_CGA = 0,
335 GFX_MDA,
336 GFX_HERCULES,
337 GFX_EGA, /*Using IBM EGA BIOS*/
338 GFX_TVGA, /*Using Trident TVGA8900D BIOS*/
339 GFX_ET4000, /*Tseng ET4000*/
340 GFX_ET4000W32, /*Tseng ET4000/W32p (Diamond Stealth 32)*/
341 GFX_BAHAMAS64, /*S3 Vision864 (Paradise Bahamas 64)*/
342 GFX_N9_9FX, /*S3 764/Trio64 (Number Nine 9FX)*/
343 GFX_VIRGE, /*S3 Virge*/
344 GFX_TGUI9440, /*Trident TGUI9440*/
345 GFX_VGA, /*IBM VGA*/
346 GFX_VGAEDGE16, /*ATI VGA Edge-16 (18800-1)*/
347 GFX_VGACHARGER, /*ATI VGA Charger (28800-5)*/
348 GFX_OTI067, /*Oak OTI-067*/
349 GFX_MACH64GX, /*ATI Graphics Pro Turbo (Mach64)*/
350 GFX_CL_GD5429, /*Cirrus Logic CL-GD5429*/
351 GFX_VIRGEDX, /*S3 Virge/DX*/
352 GFX_PHOENIX_TRIO32, /*S3 732/Trio32 (Phoenix)*/
353 GFX_PHOENIX_TRIO64, /*S3 764/Trio64 (Phoenix)*/
355 GFX_MAX
356 };
358 extern int gfx_present[GFX_MAX];
360 int gfxcard;
362 int cpuspeed;
365 /*Video*/
366 void (*pollvideo)();
367 void pollega();
368 int readflash;
369 uint8_t hercctrl;
370 int slowega,egacycles,egacycles2;
371 extern uint8_t gdcreg[16];
372 extern int egareads,egawrites;
373 extern int cga_comp;
374 extern int vid_resize;
375 extern int vid_api;
376 extern int winsizex,winsizey;
377 extern int chain4;
379 uint8_t readvram(uint16_t addr);
380 void writevram(uint16_t addr, uint8_t val);
381 void writevramgen(uint16_t addr, uint8_t val);
383 uint8_t readtandyvram(uint16_t addr);
384 void writetandy(uint16_t addr, uint8_t val);
385 void writetandyvram(uint16_t addr, uint8_t val);
387 extern int et4k_b8000;
388 extern int changeframecount;
389 extern uint8_t changedvram[(8192*1024)/1024];
391 void writeega_chain4(uint32_t addr, uint8_t val);
392 extern uint32_t svgarbank,svgawbank;
394 /*Serial*/
395 extern int mousedelay;
398 /*Sound*/
399 uint8_t spkstat;
401 float spktime;
402 int rtctime;
403 int soundtime,gustime,gustime2,vidtime;
404 int ppispeakon;
405 float CGACONST;
406 float MDACONST;
407 float VGACONST1,VGACONST2;
408 float RTCCONST;
409 int gated,speakval,speakon;
411 #define SOUNDBUFLEN (48000/10)
414 /*Sound Blaster*/
415 /*int sbenable,sblatchi,sblatcho,sbcount,sb_enable_i,sb_count_i;
416 int16_t sbdat;*/
417 void setsbclock(float clock);
419 #define SADLIB 1 /*No DSP*/
420 #define SB1 2 /*DSP v1.05*/
421 #define SB15 3 /*DSP v2.00*/
422 #define SB2 4 /*DSP v2.01 - needed for high-speed DMA*/
423 #define SBPRO 5 /*DSP v3.00*/
424 #define SBPRO2 6 /*DSP v3.02 + OPL3*/
425 #define SB16 7 /*DSP v4.05 + OPL3*/
426 #define SADGOLD 8 /*AdLib Gold*/
427 #define SND_WSS 9 /*Windows Sound System*/
428 #define SND_PAS16 10 /*Pro Audio Spectrum 16*/
430 int sbtype;
432 int clocks[3][12][4];
433 int at70hz;
435 char pcempath[512];
438 /*Hard disc*/
440 typedef struct
441 {
442 FILE *f;
443 int spt,hpc; /*Sectors per track, heads per cylinder*/
444 int tracks;
445 } PcemHDC;
447 PcemHDC hdc[2];
449 /*Keyboard*/
450 int keybsenddelay;
453 /*CD-ROM*/
454 extern int cdrom_drive;
455 extern int idecallback[2];
456 extern int cdrom_enabled;
458 void pclog(const char *format, ...);
459 extern int nmi;
461 extern int times;
464 extern float isa_timing, bus_timing;
466 extern int frame;
469 uint8_t *vramp;
471 uint64_t timer_read();
472 extern uint64_t timer_freq;