PCem: 47132154ffe7 src/ibm.h

PCem

view src/ibm.h @ 120:47132154ffe7

Added emulation of Phoenix Trio32. Based on patch from Battler. Paradise Bahamas 64, Number Nine 9FX and Phoenix Trio32 now have configurable memory sizes.

author	TomW
date	Wed Jul 09 21:45:42 2014 +0100
parents	e4da69090d05
children	84742b645324

line source

1 #include <stdio.h>

2 #include <stdint.h>

3 #include <string.h>

4 #define printf pclog

6 /*Memory*/

7 uint8_t *ram,*vram;

9 uint32_t rammask;

11 int readlookup[256],readlookupp[256];

12 uint32_t *readlookup2;

13 int readlnext;

14 int writelookup[256],writelookupp[256];

15 uint32_t *writelookup2;

16 int writelnext;

18 extern int mmu_perm;

20 #define readmemb(a) ((readlookup2[(a)>>12]==0xFFFFFFFF)?readmembl(a):*(uint8_t *)(readlookup2[(a) >> 12] + (a)))

21 #define readmemw(s,a) ((readlookup2[((s)+(a))>>12]==0xFFFFFFFF || (s)==0xFFFFFFFF || (((s)+(a))&0xFFF)>0xFFE)?readmemwl(s,a):*(uint16_t *)(readlookup2[((s)+(a))>>12]+(s)+(a)))

22 #define readmeml(s,a) ((readlookup2[((s)+(a))>>12]==0xFFFFFFFF || (s)==0xFFFFFFFF || (((s)+(a))&0xFFF)>0xFFC)?readmemll(s,a):*(uint32_t *)(readlookup2[((s)+(a))>>12]+(s)+(a)))

24 //#define writememb(a,v) if (writelookup2[(a)>>12]==0xFFFFFFFF) writemembl(a,v); else ram[writelookup2[(a)>>12]+((a)&0xFFF)]=v

25 //#define writememw(s,a,v) if (writelookup2[((s)+(a))>>12]==0xFFFFFFFF || (s)==0xFFFFFFFF) writememwl(s,a,v); else *((uint16_t *)(&ram[writelookup2[((s)+(a))>>12]+(((s)+(a))&0xFFF)]))=v

26 //#define writememl(s,a,v) if (writelookup2[((s)+(a))>>12]==0xFFFFFFFF || (s)==0xFFFFFFFF) writememll(s,a,v); else *((uint32_t *)(&ram[writelookup2[((s)+(a))>>12]+(((s)+(a))&0xFFF)]))=v

27 //#define readmemb(a) ((isram[((a)>>16)&255] && !(cr0>>31))?ram[a&0xFFFFFF]:readmembl(a))

28 //#define writememb(a,v) if (isram[((a)>>16)&255] && !(cr0>>31)) ram[a&0xFFFFFF]=v; else writemembl(a,v)

30 //void writememb(uint32_t addr, uint8_t val);

31 uint8_t readmembl(uint32_t addr);

32 void writemembl(uint32_t addr, uint8_t val);

33 uint8_t readmemb386l(uint32_t seg, uint32_t addr);

34 void writememb386l(uint32_t seg, uint32_t addr, uint8_t val);

35 uint16_t readmemwl(uint32_t seg, uint32_t addr);

36 void writememwl(uint32_t seg, uint32_t addr, uint16_t val);

37 uint32_t readmemll(uint32_t seg, uint32_t addr);

38 void writememll(uint32_t seg, uint32_t addr, uint32_t val);

40 uint8_t *getpccache(uint32_t a);

42 uint32_t mmutranslatereal(uint32_t addr, int rw);

44 void addreadlookup(uint32_t virt, uint32_t phys);

45 void addwritelookup(uint32_t virt, uint32_t phys);

48 /*IO*/

49 uint8_t inb(uint16_t port);

50 void outb(uint16_t port, uint8_t val);

51 uint16_t inw(uint16_t port);

52 void outw(uint16_t port, uint16_t val);

53 uint32_t inl(uint16_t port);

54 void outl(uint16_t port, uint32_t val);

56 FILE *romfopen(char *fn, char *mode);

57 extern int shadowbios,shadowbios_write;

58 extern int cache;

59 extern int mem_size;

60 extern int readlnum,writelnum;

61 extern int memwaitstate;

64 /*Processor*/

65 #define EAX regs[0].l

66 #define ECX regs[1].l

67 #define EDX regs[2].l

68 #define EBX regs[3].l

69 #define ESP regs[4].l

70 #define EBP regs[5].l

71 #define ESI regs[6].l

72 #define EDI regs[7].l

73 #define AX regs[0].w

74 #define CX regs[1].w

75 #define DX regs[2].w

76 #define BX regs[3].w

77 #define SP regs[4].w

78 #define BP regs[5].w

79 #define SI regs[6].w

80 #define DI regs[7].w

81 #define AL regs[0].b.l

82 #define AH regs[0].b.h

83 #define CL regs[1].b.l

84 #define CH regs[1].b.h

85 #define DL regs[2].b.l

86 #define DH regs[2].b.h

87 #define BL regs[3].b.l

88 #define BH regs[3].b.h

90 typedef union

92 uint32_t l;

93 uint16_t w;

94 struct

95 {

96 uint8_t l,h;

97 } b;

98 } x86reg;

100 x86reg regs[8];

101 uint16_t flags,eflags;

102 uint32_t /*cs,ds,es,ss,*/oldds,oldss,pc,olddslimit,oldsslimit,olddslimitw,oldsslimitw;

103 //uint16_t msw;

105 extern int ins,output;

106 extern int cycdiff;

108 typedef struct

110 uint32_t base;

111 uint32_t limit,limitw;

112 uint8_t access;

113 uint16_t seg;

114 } x86seg;

116 x86seg gdt,ldt,idt,tr;

117 x86seg _cs,_ds,_es,_ss,_fs,_gs;

118 x86seg _oldds;

120 uint32_t pccache;

121 uint8_t *pccache2;

122 /*Segments -

123 _cs,_ds,_es,_ss are the segment structures

124 CS,DS,ES,SS is the 16-bit data

125 cs,ds,es,ss are defines to the bases*/

126 //uint16_t CS,DS,ES,SS;

127 #define CS _cs.seg

128 #define DS _ds.seg

129 #define ES _es.seg

130 #define SS _ss.seg

131 #define FS _fs.seg

132 #define GS _gs.seg

133 #define cs _cs.base

134 #define ds _ds.base

135 #define es _es.base

136 #define ss _ss.base

137 #define fs _fs.base

138 #define gs _gs.base

140 #define CPL ((_cs.access>>5)&3)

142 void loadseg(uint16_t seg, x86seg *s);

143 void loadcs(uint16_t seg);

145 union

147 uint32_t l;

148 uint16_t w;

149 } CR0;

151 #define cr0 CR0.l

152 #define msw CR0.w

154 uint32_t cr2,cr3;

156 #define C_FLAG 0x0001

157 #define P_FLAG 0x0004

158 #define A_FLAG 0x0010

159 #define Z_FLAG 0x0040

160 #define N_FLAG 0x0080

161 #define T_FLAG 0x0100

162 #define I_FLAG 0x0200

163 #define D_FLAG 0x0400

164 #define V_FLAG 0x0800

165 #define NT_FLAG 0x4000

166 #define VM_FLAG 0x0002 /*In EFLAGS*/

168 #define WP_FLAG 0x10000 /*In CR0*/

170 #define IOPL ((flags>>12)&3)

172 #define IOPLp ((!(msw&1)) || (CPL<=IOPL))

173 //#define IOPLp 1

175 //#define IOPLV86 ((!(msw&1)) || (CPL<=IOPL))

176 extern int cycles;

177 extern int cycles_lost;

178 extern int is486;

179 extern uint8_t opcode;

180 extern int insc;

181 extern int fpucount;

182 extern float mips,flops;

183 extern int clockrate;

184 extern int cgate16;

185 extern int CPUID;

187 extern int cpl_override;

189 /*Timer*/

190 typedef struct PIT

192 uint32_t l[3];

193 int c[3];

194 uint8_t m[3];

195 uint8_t ctrl,ctrls[2];

196 int wp,rm[3],wm[3];

197 uint16_t rl[3];

198 int thit[3];

199 int delay[3];

200 int rereadlatch[3];

201 int gate[3];

202 int out[3];

203 int running[3];

204 int enabled[3];

205 int newcount[3];

206 int count[3];

207 int using_timer[3];

208 int initial[3];

209 } PIT;

211 PIT pit;

212 void setpitclock(float clock);

213 int pitcount;

215 float pit_timer0_freq();

219 /*DMA*/

220 typedef struct DMA

222 uint16_t ab[4],ac[4];

223 uint16_t cb[4];

224 int cc[4];

225 int wp;

226 uint8_t m,mode[4];

227 uint8_t page[4];

228 uint8_t stat;

229 uint8_t command;

230 } DMA;

232 DMA dma,dma16;

235 /*PPI*/

236 typedef struct PPI

238 int s2;

239 uint8_t pa,pb;

240 } PPI;

242 PPI ppi;

243 extern int key_inhibit;

246 /*PIC*/

247 typedef struct PIC

249 uint8_t icw1,mask,ins,pend,mask2;

250 int icw;

251 uint8_t vector;

252 int read;

253 } PIC;

255 PIC pic,pic2;

256 extern int pic_intpending;

257 int intcount;

260 int disctime;

261 char discfns[2][256];

262 int driveempty[2];

265 /*Config stuff*/

266 #define MDA ((gfxcard==GFX_MDA || gfxcard==GFX_HERCULES) && (romset<ROM_TANDY || romset>=ROM_IBMAT))

267 #define HERCULES (gfxcard==GFX_HERCULES && (romset<ROM_TANDY || romset>=ROM_IBMAT))

268 #define AMSTRAD (romset==ROM_PC1512 || romset==ROM_PC1640 || romset==ROM_PC3086)

269 #define AMSTRADIO (romset==ROM_PC1512 || romset==ROM_PC1640 || romset==ROM_PC200 || romset==ROM_PC2086 || romset == ROM_PC3086)

270 #define TANDY (romset==ROM_TANDY/* || romset==ROM_IBMPCJR*/)

271 #define VID_EGA (gfxcard==GFX_EGA)

272 #define EGA (romset==ROM_PC1640 || VID_EGA || VGA)

273 #define VGA ((gfxcard>=GFX_TVGA || romset==ROM_ACER386) && romset!=ROM_PC1640 && romset!=ROM_PC1512 && romset!=ROM_TANDY && romset!=ROM_PC200)

274 #define SVGA (gfxcard==GFX_ET4000 && VGA)

275 #define TRIDENT (gfxcard==GFX_TVGA && !OTI067)

276 #define OTI067 (romset==ROM_ACER386)

277 #define ET4000 (gfxcard==GFX_ET4000 && VGA)

278 #define ET4000W32 (gfxcard==GFX_ET4000W32 && VGA)

279 #define AT (romset>=ROM_IBMAT)

280 #define PCI (romset >= ROM_PCI486)

281 #define PCJR (romset == ROM_IBMPCJR)

283 #define AMIBIOS (romset==ROM_AMI386 || romset==ROM_AMI486 || romset == ROM_WIN486)

285 int GAMEBLASTER, GUS, SSI2001;

287 enum

289 ROM_IBMPC = 0, /*301 keyboard error, 131 cassette (!!!) error*/

290 ROM_IBMXT, /*301 keyboard error*/

291 ROM_IBMPCJR,

292 ROM_GENXT, /*'Generic XT BIOS'*/

293 ROM_DTKXT,

294 ROM_EUROPC,

295 ROM_OLIM24,

296 ROM_TANDY,

297 ROM_PC1512,

298 ROM_PC200,

299 ROM_PC1640,

300 ROM_PC2086,

301 ROM_PC3086,

302 ROM_IBMAT,

303 ROM_CMDPC30,

304 ROM_AMI286,

305 ROM_DELL200,

306 ROM_MISC286,

307 ROM_IBMAT386,

308 ROM_ACER386,

309 ROM_MEGAPC,

310 ROM_AMI386,

311 ROM_AMI486,

312 ROM_WIN486,

313 ROM_PCI486,

314 ROM_SIS496,

315 ROM_430VX,

316

317 ROM_MAX

320 extern int romspresent[ROM_MAX];

322 //#define ROM_IBMPCJR 5 /*Not working! ROMs are corrupt*/

323 #define is386 (romset>=ROM_IBMAT386)

324 #define is386sx 0

326 int hasfpu;

327 int romset;

329 enum

331 GFX_CGA = 0,

332 GFX_MDA,

333 GFX_HERCULES,

334 GFX_EGA, /*Using IBM EGA BIOS*/

335 GFX_TVGA, /*Using Trident TVGA8900D BIOS*/

336 GFX_ET4000, /*Tseng ET4000*/

337 GFX_ET4000W32, /*Tseng ET4000/W32p (Diamond Stealth 32)*/

338 GFX_BAHAMAS64, /*S3 Vision864 (Paradise Bahamas 64)*/

339 GFX_N9_9FX, /*S3 764/Trio64 (Number Nine 9FX)*/

340 GFX_VIRGE, /*S3 Virge*/

341 GFX_TGUI9440, /*Trident TGUI9440*/

342 GFX_VGA, /*IBM VGA*/

343 GFX_VGAEDGE16, /*ATI VGA Edge-16 (18800-1)*/

344 GFX_VGACHARGER, /*ATI VGA Charger (28800-5)*/

345 GFX_OTI067, /*Oak OTI-067*/

346 GFX_MACH64GX, /*ATI Graphics Pro Turbo (Mach64)*/

347 GFX_CL_GD5429, /*Cirrus Logic CL-GD5429*/

348 GFX_VIRGEDX, /*S3 Virge/DX*/

349 GFX_PHOENIX_TRIO32, /*S3 732/Trio32 (Phoenix)*/

350

351 GFX_MAX

354 extern int gfx_present[GFX_MAX];

356 int gfxcard;

358 int cpuspeed;

361 /*Video*/

362 void (*pollvideo)();

363 void pollega();

364 int readflash;

365 uint8_t hercctrl;

366 int slowega,egacycles,egacycles2;

367 extern uint8_t gdcreg[16];

368 extern int egareads,egawrites;

369 extern int cga_comp;

370 extern int vid_resize;

371 extern int vid_api;

372 extern int winsizex,winsizey;

373 extern int chain4;

375 uint8_t readvram(uint16_t addr);

376 void writevram(uint16_t addr, uint8_t val);

377 void writevramgen(uint16_t addr, uint8_t val);

379 uint8_t readtandyvram(uint16_t addr);

380 void writetandy(uint16_t addr, uint8_t val);

381 void writetandyvram(uint16_t addr, uint8_t val);

383 extern int et4k_b8000;

384 extern int changeframecount;

385 extern uint8_t changedvram[(8192*1024)/1024];

387 void writeega_chain4(uint32_t addr, uint8_t val);

388 extern uint32_t svgarbank,svgawbank;

390 /*Serial*/

391 extern int mousedelay;

394 /*Sound*/

395 uint8_t spkstat;

397 float spktime;

398 int rtctime;

399 int soundtime,gustime,gustime2,vidtime;

400 int ppispeakon;

401 float CGACONST;

402 float MDACONST;

403 float VGACONST1,VGACONST2;

404 float RTCCONST;

405 int gated,speakval,speakon;

407 #define SOUNDBUFLEN (48000/10)

410 /*Sound Blaster*/

411 /*int sbenable,sblatchi,sblatcho,sbcount,sb_enable_i,sb_count_i;

412 int16_t sbdat;*/

413 void setsbclock(float clock);

415 #define SADLIB 1 /*No DSP*/

416 #define SB1 2 /*DSP v1.05*/

417 #define SB15 3 /*DSP v2.00*/

418 #define SB2 4 /*DSP v2.01 - needed for high-speed DMA*/

419 #define SBPRO 5 /*DSP v3.00*/

420 #define SBPRO2 6 /*DSP v3.02 + OPL3*/

421 #define SB16 7 /*DSP v4.05 + OPL3*/

422 #define SADGOLD 8 /*AdLib Gold*/

423 #define SND_WSS 9 /*Windows Sound System*/

424 #define SND_PAS16 10 /*Pro Audio Spectrum 16*/

426 int sbtype;

428 int clocks[3][12][4];

429 int at70hz;

431 char pcempath[512];

434 /*Hard disc*/

436 typedef struct

438 FILE *f;

439 int spt,hpc; /*Sectors per track, heads per cylinder*/

440 int tracks;

441 } PcemHDC;

443 PcemHDC hdc[2];

445 /*Keyboard*/

446 int keybsenddelay;

449 /*CD-ROM*/

450 extern int cdrom_drive;

451 extern int idecallback[2];

452 extern int cdrom_enabled;

454 void pclog(const char *format, ...);

455 extern int nmi;

457 extern int times;

460 extern float isa_timing, bus_timing;

462 extern int frame;

465 uint8_t *vramp;

467 uint64_t timer_read();

468 extern uint64_t timer_freq;